1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (C) 2023 Nuvoton Technologies. 4 * Author: Chi-Fen Li <cfli0@nuvoton.com> 5 * 6 * Device Tree binding constants for MA35D1 reset controller. 7 */ 8 9 #ifndef __DT_BINDINGS_RESET_MA35D1_H 10 #define __DT_BINDINGS_RESET_MA35D1_H 11 12 #define MA35D1_RESET_CHIP 0 13 #define MA35D1_RESET_CA35CR0 1 14 #define MA35D1_RESET_CA35CR1 2 15 #define MA35D1_RESET_CM4 3 16 #define MA35D1_RESET_PDMA0 4 17 #define MA35D1_RESET_PDMA1 5 18 #define MA35D1_RESET_PDMA2 6 19 #define MA35D1_RESET_PDMA3 7 20 #define MA35D1_RESET_DISP 8 21 #define MA35D1_RESET_VCAP0 9 22 #define MA35D1_RESET_VCAP1 10 23 #define MA35D1_RESET_GFX 11 24 #define MA35D1_RESET_VDEC 12 25 #define MA35D1_RESET_WHC0 13 26 #define MA35D1_RESET_WHC1 14 27 #define MA35D1_RESET_GMAC0 15 28 #define MA35D1_RESET_GMAC1 16 29 #define MA35D1_RESET_HWSEM 17 30 #define MA35D1_RESET_EBI 18 31 #define MA35D1_RESET_HSUSBH0 19 32 #define MA35D1_RESET_HSUSBH1 20 33 #define MA35D1_RESET_HSUSBD 21 34 #define MA35D1_RESET_USBHL 22 35 #define MA35D1_RESET_SDH0 23 36 #define MA35D1_RESET_SDH1 24 37 #define MA35D1_RESET_NAND 25 38 #define MA35D1_RESET_GPIO 26 39 #define MA35D1_RESET_MCTLP 27 40 #define MA35D1_RESET_MCTLC 28 41 #define MA35D1_RESET_DDRPUB 29 42 #define MA35D1_RESET_TMR0 30 43 #define MA35D1_RESET_TMR1 31 44 #define MA35D1_RESET_TMR2 32 45 #define MA35D1_RESET_TMR3 33 46 #define MA35D1_RESET_I2C0 34 47 #define MA35D1_RESET_I2C1 35 48 #define MA35D1_RESET_I2C2 36 49 #define MA35D1_RESET_I2C3 37 50 #define MA35D1_RESET_QSPI0 38 51 #define MA35D1_RESET_SPI0 39 52 #define MA35D1_RESET_SPI1 40 53 #define MA35D1_RESET_SPI2 41 54 #define MA35D1_RESET_UART0 42 55 #define MA35D1_RESET_UART1 43 56 #define MA35D1_RESET_UART2 44 57 #define MA35D1_RESET_UART3 45 58 #define MA35D1_RESET_UART4 46 59 #define MA35D1_RESET_UART5 47 60 #define MA35D1_RESET_UART6 48 61 #define MA35D1_RESET_UART7 49 62 #define MA35D1_RESET_CANFD0 50 63 #define MA35D1_RESET_CANFD1 51 64 #define MA35D1_RESET_EADC0 52 65 #define MA35D1_RESET_I2S0 53 66 #define MA35D1_RESET_SC0 54 67 #define MA35D1_RESET_SC1 55 68 #define MA35D1_RESET_QSPI1 56 69 #define MA35D1_RESET_SPI3 57 70 #define MA35D1_RESET_EPWM0 58 71 #define MA35D1_RESET_EPWM1 59 72 #define MA35D1_RESET_QEI0 60 73 #define MA35D1_RESET_QEI1 61 74 #define MA35D1_RESET_ECAP0 62 75 #define MA35D1_RESET_ECAP1 63 76 #define MA35D1_RESET_CANFD2 64 77 #define MA35D1_RESET_ADC0 65 78 #define MA35D1_RESET_TMR4 66 79 #define MA35D1_RESET_TMR5 67 80 #define MA35D1_RESET_TMR6 68 81 #define MA35D1_RESET_TMR7 69 82 #define MA35D1_RESET_TMR8 70 83 #define MA35D1_RESET_TMR9 71 84 #define MA35D1_RESET_TMR10 72 85 #define MA35D1_RESET_TMR11 73 86 #define MA35D1_RESET_UART8 74 87 #define MA35D1_RESET_UART9 75 88 #define MA35D1_RESET_UART10 76 89 #define MA35D1_RESET_UART11 77 90 #define MA35D1_RESET_UART12 78 91 #define MA35D1_RESET_UART13 79 92 #define MA35D1_RESET_UART14 80 93 #define MA35D1_RESET_UART15 81 94 #define MA35D1_RESET_UART16 82 95 #define MA35D1_RESET_I2S1 83 96 #define MA35D1_RESET_I2C4 84 97 #define MA35D1_RESET_I2C5 85 98 #define MA35D1_RESET_EPWM2 86 99 #define MA35D1_RESET_ECAP2 87 100 #define MA35D1_RESET_QEI2 88 101 #define MA35D1_RESET_CANFD3 89 102 #define MA35D1_RESET_KPI 90 103 #define MA35D1_RESET_GIC 91 104 #define MA35D1_RESET_SSMCC 92 105 #define MA35D1_RESET_SSPCC 93 106 #define MA35D1_RESET_COUNT 94 107 108 #endif 109