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Searched refs:LoongArch (Results 1 – 25 of 68) sorted by relevance

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/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaLoongArch.cpp29 case LoongArch::BI__builtin_loongarch_cacop_d: in CheckLoongArchBuiltinFunctionCall()
30 case LoongArch::BI__builtin_loongarch_cacop_w: { in CheckLoongArchBuiltinFunctionCall()
35 case LoongArch::BI__builtin_loongarch_break: in CheckLoongArchBuiltinFunctionCall()
36 case LoongArch::BI__builtin_loongarch_dbar: in CheckLoongArchBuiltinFunctionCall()
37 case LoongArch::BI__builtin_loongarch_ibar: in CheckLoongArchBuiltinFunctionCall()
38 case LoongArch::BI__builtin_loongarch_syscall: in CheckLoongArchBuiltinFunctionCall()
41 case LoongArch::BI__builtin_loongarch_csrrd_w: in CheckLoongArchBuiltinFunctionCall()
42 case LoongArch::BI__builtin_loongarch_csrrd_d: in CheckLoongArchBuiltinFunctionCall()
44 case LoongArch::BI__builtin_loongarch_csrwr_w: in CheckLoongArchBuiltinFunctionCall()
45 case LoongArch::BI__builtin_loongarch_csrwr_d: in CheckLoongArchBuiltinFunctionCall()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchOptWInstrs.cpp131 case LoongArch::ADD_W: in hasAllNBitUsers()
132 case LoongArch::ADDI_W: in hasAllNBitUsers()
133 case LoongArch::SUB_W: in hasAllNBitUsers()
134 case LoongArch::ALSL_W: in hasAllNBitUsers()
135 case LoongArch::ALSL_WU: in hasAllNBitUsers()
136 case LoongArch::MUL_W: in hasAllNBitUsers()
137 case LoongArch::MULH_W: in hasAllNBitUsers()
138 case LoongArch::MULH_WU: in hasAllNBitUsers()
139 case LoongArch::MULW_D_W: in hasAllNBitUsers()
140 case LoongArch::MULW_D_WU: in hasAllNBitUsers()
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H A DLoongArchMergeBaseOffset.cpp105 if (Hi20.getOpcode() != LoongArch::PCALAU12I) in INITIALIZE_PASS()
124 if (UseInst->getOpcode() != LoongArch::ADD_D) { in INITIALIZE_PASS()
126 if ((ST->is64Bit() && Lo12->getOpcode() != LoongArch::ADDI_D) || in INITIALIZE_PASS()
127 (!ST->is64Bit() && Lo12->getOpcode() != LoongArch::ADDI_W)) in INITIALIZE_PASS()
160 assert(Hi20.getOpcode() == LoongArch::PCALAU12I); in INITIALIZE_PASS()
197 if (Hi20.getOpcode() != LoongArch::LU12I_W) in detectFoldable()
214 if ((ST->is64Bit() && Add->getOpcode() != LoongArch::PseudoAddTPRel_D) || in detectFoldable()
215 (!ST->is64Bit() && Add->getOpcode() != LoongArch::PseudoAddTPRel_W)) in detectFoldable()
218 if (Add->getOperand(2).getReg() != LoongArch::R2) in detectFoldable()
232 if ((ST->is64Bit() && Lo12->getOpcode() != LoongArch::ADDI_D) || in detectFoldable()
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H A DLoongArchInstrInfo.cpp29 : LoongArchGenInstrInfo(LoongArch::ADJCALLSTACKDOWN, in LoongArchInstrInfo()
30 LoongArch::ADJCALLSTACKUP), in LoongArchInstrInfo()
34 return MCInstBuilder(LoongArch::ANDI) in getNop()
35 .addReg(LoongArch::R0) in getNop()
36 .addReg(LoongArch::R0) in getNop()
46 if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
47 BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg) in copyPhysReg()
49 .addReg(LoongArch::R0); in copyPhysReg()
54 if (LoongArch::LSX128RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
55 BuildMI(MBB, MBBI, DL, get(LoongArch::VORI_B), DstReg) in copyPhysReg()
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H A DLoongArchExpandAtomicPseudoInsts.cpp92 case LoongArch::PseudoMaskedAtomicSwap32: in expandMI()
95 case LoongArch::PseudoAtomicSwap32: in expandMI()
98 case LoongArch::PseudoMaskedAtomicLoadAdd32: in expandMI()
100 case LoongArch::PseudoMaskedAtomicLoadSub32: in expandMI()
102 case LoongArch::PseudoAtomicLoadNand32: in expandMI()
105 case LoongArch::PseudoAtomicLoadNand64: in expandMI()
108 case LoongArch::PseudoMaskedAtomicLoadNand32: in expandMI()
111 case LoongArch::PseudoAtomicLoadAdd32: in expandMI()
114 case LoongArch::PseudoAtomicLoadSub32: in expandMI()
117 case LoongArch::PseudoAtomicLoadAnd32: in expandMI()
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H A DLoongArchExpandPseudoInsts.cpp138 case LoongArch::PseudoLA_PCREL: in expandMI()
140 case LoongArch::PseudoLA_PCREL_LARGE: in expandMI()
142 case LoongArch::PseudoLA_GOT: in expandMI()
144 case LoongArch::PseudoLA_GOT_LARGE: in expandMI()
146 case LoongArch::PseudoLA_TLS_LE: in expandMI()
148 case LoongArch::PseudoLA_TLS_IE: in expandMI()
150 case LoongArch::PseudoLA_TLS_IE_LARGE: in expandMI()
152 case LoongArch::PseudoLA_TLS_LD: in expandMI()
154 case LoongArch::PseudoLA_TLS_LD_LARGE: in expandMI()
156 case LoongArch::PseudoLA_TLS_GD: in expandMI()
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H A DLoongArchRegisterInfo.cpp34 : LoongArchGenRegisterInfo(LoongArch::R1, /*DwarfFlavour*/ 0, in LoongArchRegisterInfo()
91 markSuperRegs(Reserved, LoongArch::R0); // zero in getReservedRegs()
92 markSuperRegs(Reserved, LoongArch::R2); // tp in getReservedRegs()
93 markSuperRegs(Reserved, LoongArch::R3); // sp in getReservedRegs()
94 markSuperRegs(Reserved, LoongArch::R21); // non-allocatable in getReservedRegs()
96 markSuperRegs(Reserved, LoongArch::R22); // fp in getReservedRegs()
109 return TFI->hasFP(MF) ? LoongArch::R22 : LoongArch::R3; in getFrameRegister()
148 case LoongArch::VSTELM_B: in eliminateFrameIndex()
149 case LoongArch::XVSTELM_B: in eliminateFrameIndex()
152 case LoongArch::VSTELM_H: in eliminateFrameIndex()
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H A DLoongArchAsmPrinter.cpp91 OS << '$' << LoongArchInstPrinter::getRegisterName(LoongArch::R0); in PrintAsmOperand()
102 if (RegID >= LoongArch::XR0 && RegID <= LoongArch::XR31) in PrintAsmOperand()
103 FirstReg = LoongArch::XR0; in PrintAsmOperand()
104 else if (RegID >= LoongArch::VR0 && RegID <= LoongArch::VR31) in PrintAsmOperand()
105 FirstReg = LoongArch::VR0; in PrintAsmOperand()
106 else if (RegID >= LoongArch::F0_64 && RegID <= LoongArch::F31_64) in PrintAsmOperand()
107 FirstReg = LoongArch::F0_64; in PrintAsmOperand()
108 else if (RegID >= LoongArch::F0 && RegID <= LoongArch::F31) in PrintAsmOperand()
109 FirstReg = LoongArch::F0; in PrintAsmOperand()
115 (ExtraCode[0] == 'u' ? LoongArch::XR0 : LoongArch::VR0)); in PrintAsmOperand()
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H A DLoongArchFrameLowering.cpp57 unsigned Addi = IsLA64 ? LoongArch::ADDI_D : LoongArch::ADDI_W; in adjustReg()
93 unsigned Opc = IsLA64 ? LoongArch::ADD_D : LoongArch::ADD_W; in adjustReg()
96 Opc = IsLA64 ? LoongArch::SUB_D : LoongArch::SUB_W; in adjustReg()
100 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass); in adjustReg()
136 if (MI.getOpcode() == LoongArch::PseudoST_CFR) in needScavSlotForCFR()
144 const TargetRegisterClass &RC = LoongArch::GPRRegClass; in processFunctionBeforeFrameFinalized()
194 Register SPReg = LoongArch::R3; in emitPrologue()
195 Register FPReg = LoongArch::R22; in emitPrologue()
289 TII->get(IsLA64 ? LoongArch::BSTRINS_D : LoongArch::BSTRINS_W), in emitPrologue()
292 .addReg(LoongArch::R0) in emitPrologue()
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H A DLoongArchISelDAGToDAG.cpp57 LoongArch::R0, GRLenVT); in INITIALIZE_PASS()
62 SDValue SrcReg = CurDAG->getRegister(LoongArch::R0, GRLenVT); in INITIALIZE_PASS()
67 case LoongArch::LU12I_W: in INITIALIZE_PASS()
70 case LoongArch::ADDI_W: in INITIALIZE_PASS()
71 case LoongArch::ORI: in INITIALIZE_PASS()
72 case LoongArch::LU32I_D: in INITIALIZE_PASS()
73 case LoongArch::LU52I_D: in INITIALIZE_PASS()
76 case LoongArch::BSTRINS_D: in INITIALIZE_PASS()
97 Subtarget->is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; in INITIALIZE_PASS()
131 Op = Is256Vec ? LoongArch::PseudoXVREPLI_B : LoongArch::PseudoVREPLI_B; in INITIALIZE_PASS()
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H A DLoongArchISelDAGToDAG.h76 return LoongArch::BEQ; in getBranchOpcForIntCC()
78 return LoongArch::BNE; in getBranchOpcForIntCC()
80 return LoongArch::BLT; in getBranchOpcForIntCC()
82 return LoongArch::BGE; in getBranchOpcForIntCC()
84 return LoongArch::BLTU; in getBranchOpcForIntCC()
86 return LoongArch::BGEU; in getBranchOpcForIntCC()
H A DLoongArchISelLowering.cpp55 addRegisterClass(GRLenVT, &LoongArch::GPRRegClass); in LoongArchTargetLowering()
57 addRegisterClass(MVT::f32, &LoongArch::FPR32RegClass); in LoongArchTargetLowering()
59 addRegisterClass(MVT::f64, &LoongArch::FPR64RegClass); in LoongArchTargetLowering()
68 addRegisterClass(VT, &LoongArch::LSX128RegClass); in LoongArchTargetLowering()
72 addRegisterClass(VT, &LoongArch::LASX256RegClass); in LoongArchTargetLowering()
418 setStackPointerRegisterToSaveRestore(LoongArch::R3); in LoongArchTargetLowering()
2871 Load = SDValue(DAG.getMachineNode(LoongArch::PseudoLA_PCREL_LARGE, DL, Ty, in getAddr()
2878 DAG.getMachineNode(LoongArch::PseudoLA_GOT_LARGE, DL, Ty, Tmp, Addr), in getAddr()
2890 DAG.getMachineNode(LoongArch::PseudoLA_PCREL, DL, Ty, Addr), 0); in getAddr()
2895 SDValue(DAG.getMachineNode(LoongArch::PseudoLA_GOT, DL, Ty, Addr), 0); in getAddr()
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H A DLoongArchRegisterInfo.td1 //===-- LoongArchRegisterInfo.td - LoongArch Register defs -*- tablegen -*-===//
10 // Declarations that describe the LoongArch register files
13 let Namespace = "LoongArch" in {
54 } // Namespace = "LoongArch"
101 : RegisterClass<"LoongArch", [GRLenVT], 32, regList> {
178 def FPR32 : RegisterClass<"LoongArch", [f32], 32, (sequence "F%u", 0, 31)>;
179 def FPR64 : RegisterClass<"LoongArch", [f64], 64, (sequence "F%u_64", 0, 31)>;
186 def CFR : RegisterClass<"LoongArch", [GRLenVT], 32, (sequence "FCC%u", 0, 7)> {
196 def FCSR : RegisterClass<"LoongArch", [i32], 32, (sequence "FCSR%u", 0, 3)>;
204 def LSX128 : RegisterClass<"LoongArch",
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H A DLoongArch.td1 //===-- LoongArch.td - Describe the LoongArch Target -------*- tablegen -*-===//
12 // LoongArch subtarget features and instruction predicates.
15 // LoongArch is divided into two versions, the 32-bit version (LA32) and the
18 // LoongArch 32-bit is divided into two variants, the reduced 32-bit variant
166 // LoongArch processors supported.
202 // Define the LoongArch target.
224 def LoongArch : Target {
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchMCCodeEmitter.cpp104 case LoongArch::fixup_loongarch_b16: in addFixup()
105 case LoongArch::fixup_loongarch_b21: in addFixup()
106 case LoongArch::fixup_loongarch_b26: in addFixup()
141 bool EnableRelax = STI.hasFeature(LoongArch::FeatureRelax); in getExprOpValue()
144 unsigned FixupKind = LoongArch::fixup_loongarch_invalid; in getExprOpValue()
156 FixupKind = LoongArch::fixup_loongarch_b16; in getExprOpValue()
159 FixupKind = LoongArch::fixup_loongarch_b21; in getExprOpValue()
162 FixupKind = LoongArch::fixup_loongarch_b26; in getExprOpValue()
165 FixupKind = LoongArch::fixup_loongarch_abs_hi20; in getExprOpValue()
168 FixupKind = LoongArch::fixup_loongarch_abs_lo12; in getExprOpValue()
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H A DLoongArchMCTargetDesc.cpp44 InitLoongArchMCRegisterInfo(X, LoongArch::R1); in createLoongArchMCRegisterInfo()
67 unsigned SP = MRI.getDwarfRegNum(LoongArch::R3, true); in createLoongArchMCAsmInfo()
106 Inst.getOpcode() == LoongArch::BL) { in evaluateBranch()
121 case LoongArch::JIRL: in isTerminator()
122 return Inst.getOperand(0).getReg() == LoongArch::R0; in isTerminator()
133 case LoongArch::JIRL: in isCall()
134 return Inst.getOperand(0).getReg() != LoongArch::R0; in isCall()
145 case LoongArch::JIRL: in isReturn()
146 return Inst.getOperand(0).getReg() == LoongArch::R0 && in isReturn()
147 Inst.getOperand(1).getReg() == LoongArch::R1; in isReturn()
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H A DLoongArchMatInt.cpp31 Insts.push_back(Inst(LoongArch::LU52I_D, SignExtend64<12>(Highest12))); in generateInstSeq()
37 Insts.push_back(Inst(LoongArch::ORI, Lo12)); in generateInstSeq()
39 Insts.push_back(Inst(LoongArch::ADDI_W, SignExtend64<12>(Lo12))); in generateInstSeq()
41 Insts.push_back(Inst(LoongArch::LU12I_W, SignExtend64<20>(Hi20))); in generateInstSeq()
43 Insts.push_back(Inst(LoongArch::ORI, Lo12)); in generateInstSeq()
49 Insts.push_back(Inst(LoongArch::LU32I_D, SignExtend64<20>(Higher20))); in generateInstSeq()
53 Insts.push_back(Inst(LoongArch::LU52I_D, SignExtend64<12>(Highest12))); in generateInstSeq()
80 case LoongArch::LU12I_W: in generateInstSeq()
81 if (Insts[1].Opc == LoongArch::ORI) { in generateInstSeq()
89 case LoongArch::ORI: in generateInstSeq()
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H A DLoongArchELFObjectWriter.cpp88 case LoongArch::fixup_loongarch_b16: in getRelocType()
90 case LoongArch::fixup_loongarch_b21: in getRelocType()
92 case LoongArch::fixup_loongarch_b26: in getRelocType()
94 case LoongArch::fixup_loongarch_abs_hi20: in getRelocType()
96 case LoongArch::fixup_loongarch_abs_lo12: in getRelocType()
98 case LoongArch::fixup_loongarch_abs64_lo20: in getRelocType()
100 case LoongArch::fixup_loongarch_abs64_hi12: in getRelocType()
H A DLoongArchBaseInfo.cpp88 return !Is64Bit && FeatureBits[LoongArch::FeatureBasicF]; in computeTargetABI()
90 return !Is64Bit && FeatureBits[LoongArch::FeatureBasicD]; in computeTargetABI()
94 return Is64Bit && FeatureBits[LoongArch::FeatureBasicF]; in computeTargetABI()
96 return Is64Bit && FeatureBits[LoongArch::FeatureBasicD]; in computeTargetABI()
164 if (FeatureBits[LoongArch::FeatureBasicD]) in computeTargetABI()
166 if (FeatureBits[LoongArch::FeatureBasicF]) in computeTargetABI()
191 MCRegister getBPReg() { return LoongArch::R31; } in getBPReg()
H A DLoongArchAsmBackend.cpp69 static_assert((std::size(Infos)) == LoongArch::NumTargetFixupKinds, in getFixupKindInfo()
81 LoongArch::NumTargetFixupKinds && in getFixupKindInfo()
102 case LoongArch::fixup_loongarch_b16: { in adjustFixupValue()
109 case LoongArch::fixup_loongarch_b21: { in adjustFixupValue()
116 case LoongArch::fixup_loongarch_b26: { in adjustFixupValue()
123 case LoongArch::fixup_loongarch_abs_hi20: in adjustFixupValue()
125 case LoongArch::fixup_loongarch_abs_lo12: in adjustFixupValue()
127 case LoongArch::fixup_loongarch_abs64_lo20: in adjustFixupValue()
129 case LoongArch::fixup_loongarch_abs64_hi12: in adjustFixupValue()
187 if (!AF.getSubtargetInfo()->hasFeature(LoongArch::FeatureRelax)) in shouldInsertExtraNopBytesForCodeAlign()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp40 bool is64Bit() const { return getSTI().hasFeature(LoongArch::Feature64Bit); } in is64Bit()
240 LoongArchMCRegisterClasses[LoongArch::GPRRegClassID].contains( in isGPR()
631 assert(Reg >= LoongArch::F0 && Reg <= LoongArch::F31 && "Invalid register"); in convertFPR32ToFPR64()
632 return Reg - LoongArch::F0 + LoongArch::F0_64; in convertFPR32ToFPR64()
642 assert(!(RegNo >= LoongArch::F0_64 && RegNo <= LoongArch::F31_64)); in matchRegisterNameHelper()
644 static_assert(LoongArch::F0 < LoongArch::F0_64, in matchRegisterNameHelper()
646 if (RegNo == LoongArch::NoRegister) in matchRegisterNameHelper()
649 return RegNo == LoongArch::NoRegister; in matchRegisterNameHelper()
657 if (!LoongArchMCRegisterClasses[LoongArch::GPRRegClassID].contains(Reg) && in parseRegister()
658 !LoongArchMCRegisterClasses[LoongArch::FPR32RegClassID].contains(Reg)) in parseRegister()
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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DLoongArchTargetParser.cpp18 using namespace llvm::LoongArch;
27 {NAME, LoongArch::ArchKind::KIND, FEATURES},
31 bool LoongArch::isValidArchName(StringRef Arch) { in isValidArchName()
38 bool LoongArch::isValidFeatureName(StringRef Feature) { in isValidFeatureName()
50 bool LoongArch::getArchFeatures(StringRef Arch, in getArchFeatures()
80 bool LoongArch::isValidCPUName(StringRef Name) { return isValidArchName(Name); } in isValidCPUName()
82 void LoongArch::fillValidCPUList(SmallVectorImpl<StringRef> &Values) { in fillValidCPUList()
87 StringRef LoongArch::getDefaultArch(bool Is64Bit) { in getDefaultArch()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/Disassembler/
H A DLoongArchDisassembler.cpp63 Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo)); in DecodeGPRRegisterClass()
80 Inst.addOperand(MCOperand::createReg(LoongArch::F0 + RegNo)); in DecodeFPR32RegisterClass()
89 Inst.addOperand(MCOperand::createReg(LoongArch::F0_64 + RegNo)); in DecodeFPR64RegisterClass()
98 Inst.addOperand(MCOperand::createReg(LoongArch::FCC0 + RegNo)); in DecodeCFRRegisterClass()
107 Inst.addOperand(MCOperand::createReg(LoongArch::FCSR0 + RegNo)); in DecodeFCSRRegisterClass()
116 Inst.addOperand(MCOperand::createReg(LoongArch::VR0 + RegNo)); in DecodeLSX128RegisterClass()
125 Inst.addOperand(MCOperand::createReg(LoongArch::XR0 + RegNo)); in DecodeLASX256RegisterClass()
134 Inst.addOperand(MCOperand::createReg(LoongArch::SCR0 + RegNo)); in DecodeSCRRegisterClass()
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DLoongArch.cpp289 LoongArch::FirstLSXBuiltin - Builtin::FirstTSBuiltin;
291 LoongArch::FirstLASXBuiltin - LoongArch::FirstLSXBuiltin;
293 LoongArch::LastTSBuiltin - LoongArch::FirstLASXBuiltin;
295 LoongArch::LastTSBuiltin - Builtin::FirstTSBuiltin;
431 if (llvm::LoongArch::isValidArchName(Value) || Value == "la64v1.0" || in parseTargetAttr()
434 if (llvm::LoongArch::getArchFeatures(Value, ArchFeatures)) { in parseTargetAttr()
473 return llvm::LoongArch::isValidCPUName(Name); in isValidCPUName()
478 llvm::LoongArch::fillValidCPUList(Values); in fillValidCPUList()
482 return llvm::LoongArch::isValidFeatureName(Name); in isValidFeatureName()
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ELFRelocs/
H A DLoongArch.def5 // These types and values are from the LoongArch ELF psABI which can be found at
6 // https://github.com/loongson/LoongArch-Documentation
66 // Spec addition: https://github.com/loongson/LoongArch-Documentation/pull/57
107 // Relocs added in ELF for the LoongArch™ Architecture v20230519, part of the
108 // v2.10 LoongArch ABI specs.
124 // Relocs added in ELF for the LoongArch™ Architecture v20231102, part of the
125 // v2.20 LoongArch ABI specs.
130 // Relocs added in ELF for the LoongArch™ Architecture v20231219, part of the
131 // v2.30 LoongArch ABI specs.

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