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Searched refs:LoongArch (Results 1 – 25 of 58) sorted by relevance

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/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaLoongArch.cpp29 case LoongArch::BI__builtin_loongarch_cacop_d: in CheckLoongArchBuiltinFunctionCall()
30 case LoongArch::BI__builtin_loongarch_cacop_w: { in CheckLoongArchBuiltinFunctionCall()
36 case LoongArch::BI__builtin_loongarch_break: in CheckLoongArchBuiltinFunctionCall()
37 case LoongArch::BI__builtin_loongarch_dbar: in CheckLoongArchBuiltinFunctionCall()
38 case LoongArch::BI__builtin_loongarch_ibar: in CheckLoongArchBuiltinFunctionCall()
39 case LoongArch::BI__builtin_loongarch_syscall: in CheckLoongArchBuiltinFunctionCall()
42 case LoongArch::BI__builtin_loongarch_csrrd_w: in CheckLoongArchBuiltinFunctionCall()
43 case LoongArch::BI__builtin_loongarch_csrrd_d: in CheckLoongArchBuiltinFunctionCall()
45 case LoongArch::BI__builtin_loongarch_csrwr_w: in CheckLoongArchBuiltinFunctionCall()
46 case LoongArch::BI__builtin_loongarch_csrwr_d: in CheckLoongArchBuiltinFunctionCall()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchOptWInstrs.cpp132 case LoongArch::ADD_W: in hasAllNBitUsers()
133 case LoongArch::ADDI_W: in hasAllNBitUsers()
134 case LoongArch::SUB_W: in hasAllNBitUsers()
135 case LoongArch::ALSL_W: in hasAllNBitUsers()
136 case LoongArch::ALSL_WU: in hasAllNBitUsers()
137 case LoongArch::MUL_W: in hasAllNBitUsers()
138 case LoongArch::MULH_W: in hasAllNBitUsers()
139 case LoongArch::MULH_WU: in hasAllNBitUsers()
140 case LoongArch::MULW_D_W: in hasAllNBitUsers()
141 case LoongArch::MULW_D_WU: in hasAllNBitUsers()
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H A DLoongArchInstrInfo.cpp28 : LoongArchGenInstrInfo(LoongArch::ADJCALLSTACKDOWN, in LoongArchInstrInfo()
29 LoongArch::ADJCALLSTACKUP), in LoongArchInstrInfo()
33 return MCInstBuilder(LoongArch::ANDI) in getNop()
34 .addReg(LoongArch::R0) in getNop()
35 .addReg(LoongArch::R0) in getNop()
43 if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
44 BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg) in copyPhysReg()
46 .addReg(LoongArch::R0); in copyPhysReg()
51 if (LoongArch::LSX128RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
52 BuildMI(MBB, MBBI, DL, get(LoongArch::VORI_B), DstReg) in copyPhysReg()
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H A DLoongArchExpandPseudoInsts.cpp116 case LoongArch::PseudoLA_PCREL: in expandMI()
118 case LoongArch::PseudoLA_GOT: in expandMI()
120 case LoongArch::PseudoLA_TLS_LE: in expandMI()
122 case LoongArch::PseudoLA_TLS_IE: in expandMI()
124 case LoongArch::PseudoLA_TLS_LD: in expandMI()
126 case LoongArch::PseudoLA_TLS_GD: in expandMI()
128 case LoongArch::PseudoLA_TLS_DESC_PC: in expandMI()
144 MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass); in expandPcalau12iInstPair()
147 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg) in expandPcalau12iInstPair()
170 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; in expandLoadAddressPcrel()
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H A DLoongArchExpandAtomicPseudoInsts.cpp16 #include "LoongArch.h"
27 "LoongArch atomic pseudo instruction expansion pass"
91 case LoongArch::PseudoMaskedAtomicSwap32: in expandMI()
94 case LoongArch::PseudoAtomicSwap32: in expandMI()
97 case LoongArch::PseudoMaskedAtomicLoadAdd32: in expandMI()
99 case LoongArch::PseudoMaskedAtomicLoadSub32: in expandMI()
101 case LoongArch::PseudoAtomicLoadNand32: in expandMI()
104 case LoongArch::PseudoAtomicLoadNand64: in expandMI()
107 case LoongArch::PseudoMaskedAtomicLoadNand32: in expandMI()
110 case LoongArch in expandMI()
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H A DLoongArchRegisterInfo.cpp1 //===- LoongArchRegisterInfo.cpp - LoongArch Register Information -*- C++ -*-=//
9 // This file contains the LoongArch implementation of the TargetRegisterInfo
15 #include "LoongArch.h"
34 : LoongArchGenRegisterInfo(LoongArch::R1, /*DwarfFlavour*/ 0, in LoongArchRegisterInfo()
91 markSuperRegs(Reserved, LoongArch::R0); // zero in getReservedRegs()
92 markSuperRegs(Reserved, LoongArch::R2); // tp in getReservedRegs()
93 markSuperRegs(Reserved, LoongArch::R3); // sp in getReservedRegs()
94 markSuperRegs(Reserved, LoongArch::R21); // non-allocatable in getReservedRegs()
96 markSuperRegs(Reserved, LoongArch::R22); // fp in getReservedRegs()
109 return TFI->hasFP(MF) ? LoongArch in getFrameRegister()
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H A DLoongArchFrameLowering.cpp57 unsigned Addi = IsLA64 ? LoongArch::ADDI_D : LoongArch::ADDI_W; in adjustReg()
93 unsigned Opc = IsLA64 ? LoongArch::ADD_D : LoongArch::ADD_W; in adjustReg()
96 Opc = IsLA64 ? LoongArch::SUB_D : LoongArch::SUB_W; in adjustReg()
100 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass); in adjustReg()
136 if (MI.getOpcode() == LoongArch::PseudoST_CFR) in needScavSlotForCFR()
144 const TargetRegisterClass &RC = LoongArch::GPRRegClass; in processFunctionBeforeFrameFinalized()
189 Register SPReg = LoongArch::R3; in emitPrologue()
190 Register FPReg = LoongArch::R22; in emitPrologue()
284 TII->get(IsLA64 ? LoongArch::BSTRINS_D : LoongArch::BSTRINS_W), in emitPrologue()
287 .addReg(LoongArch::R0) in emitPrologue()
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H A DLoongArchISelDAGToDAG.cpp56 LoongArch::R0, GRLenVT); in INITIALIZE_PASS()
61 SDValue SrcReg = CurDAG->getRegister(LoongArch::R0, GRLenVT); in INITIALIZE_PASS()
65 if (Inst.Opc == LoongArch::LU12I_W) in INITIALIZE_PASS()
66 Result = CurDAG->getMachineNode(LoongArch::LU12I_W, DL, GRLenVT, SDImm); in INITIALIZE_PASS()
80 Subtarget->is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; in INITIALIZE_PASS()
114 Op = Is256Vec ? LoongArch::PseudoXVREPLI_B : LoongArch::PseudoVREPLI_B; in INITIALIZE_PASS()
118 Op = Is256Vec ? LoongArch::PseudoXVREPLI_H : LoongArch::PseudoVREPLI_H; in INITIALIZE_PASS()
122 Op = Is256Vec ? LoongArch::PseudoXVREPLI_W : LoongArch::PseudoVREPLI_W; in INITIALIZE_PASS()
126 Op = Is256Vec ? LoongArch::PseudoXVREPLI_D : LoongArch::PseudoVREPLI_D; in INITIALIZE_PASS()
219 Base = CurDAG->getRegister(LoongArch::R0, VT); in SelectAddrConstant()
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H A DLoongArchISelLowering.cpp53 addRegisterClass(GRLenVT, &LoongArch::GPRRegClass); in LoongArchTargetLowering()
55 addRegisterClass(MVT::f32, &LoongArch::FPR32RegClass); in LoongArchTargetLowering()
57 addRegisterClass(MVT::f64, &LoongArch::FPR64RegClass); in LoongArchTargetLowering()
66 addRegisterClass(VT, &LoongArch::LSX128RegClass); in LoongArchTargetLowering()
70 addRegisterClass(VT, &LoongArch::LASX256RegClass); in LoongArchTargetLowering()
349 setStackPointerRegisterToSaveRestore(LoongArch::R3); in LoongArchTargetLowering()
1714 Load = SDValue(DAG.getMachineNode(LoongArch::PseudoLA_PCREL_LARGE, DL, Ty, in getAddr()
1721 DAG.getMachineNode(LoongArch::PseudoLA_GOT_LARGE, DL, Ty, Tmp, Addr), in getAddr()
1733 DAG.getMachineNode(LoongArch::PseudoLA_PCREL, DL, Ty, Addr), 0); in getAddr()
1738 SDValue(DAG.getMachineNode(LoongArch::PseudoLA_GOT, DL, Ty, Addr), 0); in getAddr()
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H A DLoongArchAsmPrinter.cpp74 OS << '$' << LoongArchInstPrinter::getRegisterName(LoongArch::R0); in PrintAsmOperand()
79 if (MO.getReg().id() >= LoongArch::VR0 && in PrintAsmOperand()
80 MO.getReg().id() <= LoongArch::VR31) in PrintAsmOperand()
86 if (MO.getReg().id() >= LoongArch::XR0 && in PrintAsmOperand()
87 MO.getReg().id() <= LoongArch::XR31) in PrintAsmOperand()
183 MCInstBuilder(LoongArch::B) in emitSled()
H A DLoongArchRegisterInfo.td1 //===-- LoongArchRegisterInfo.td - LoongArch Register defs -*- tablegen -*-===//
10 // Declarations that describe the LoongArch register files
13 let Namespace = "LoongArch" in {
54 } // Namespace = "LoongArch"
102 def GPR : RegisterClass<"LoongArch", [GRLenVT], 32, (add
120 def GPRT : RegisterClass<"LoongArch", [GRLenVT], 32, (add
170 def FPR32 : RegisterClass<"LoongArch", [f32], 32, (sequence "F%u", 0, 31)>;
171 def FPR64 : RegisterClass<"LoongArch", [f64], 64, (sequence "F%u_64", 0, 31)>;
178 def CFR : RegisterClass<"LoongArch", [GRLenVT], 32, (sequence "FCC%u", 0, 7)> {
188 def FCSR : RegisterClass<"LoongArch", [i32], 32, (sequence "FCSR%u", 0, 3)>;
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H A DLoongArch.td1 //===-- LoongArch.td - Describe the LoongArch Target -------*- tablegen -*-===//
12 // LoongArch subtarget features and instruction predicates.
15 // LoongArch is divided into two versions, the 32-bit version (LA32) and the
128 // LoongArch processors supported.
157 // Define the LoongArch target.
179 def LoongArch : Target {
H A DLoongArchCallingConv.td1 //=- LoongArchCallingConv.td - Calling Conventions LoongArch -*- tablegen -*-=//
9 // This describes the calling conventions for the LoongArch architecture.
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchMCCodeEmitter.cpp129 bool EnableRelax = STI.hasFeature(LoongArch::FeatureRelax); in getExprOpValue()
132 LoongArch::Fixups FixupKind = LoongArch::fixup_loongarch_invalid; in getExprOpValue()
145 FixupKind = LoongArch::fixup_loongarch_b16; in getExprOpValue()
148 FixupKind = LoongArch::fixup_loongarch_b21; in getExprOpValue()
153 FixupKind = LoongArch::fixup_loongarch_b26; in getExprOpValue()
156 FixupKind = LoongArch::fixup_loongarch_abs_hi20; in getExprOpValue()
159 FixupKind = LoongArch::fixup_loongarch_abs_lo12; in getExprOpValue()
162 FixupKind = LoongArch::fixup_loongarch_abs64_lo20; in getExprOpValue()
165 FixupKind = LoongArch::fixup_loongarch_abs64_hi12; in getExprOpValue()
168 FixupKind = LoongArch::fixup_loongarch_pcala_hi20; in getExprOpValue()
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H A DLoongArchMCTargetDesc.cpp45 InitLoongArchMCRegisterInfo(X, LoongArch::R1); in createLoongArchMCRegisterInfo()
68 MCRegister SP = MRI.getDwarfRegNum(LoongArch::R3, true); in createLoongArchMCAsmInfo()
101 Inst.getOpcode() == LoongArch::BL) { in evaluateBranch()
116 case LoongArch::JIRL: in isTerminator()
117 return Inst.getOperand(0).getReg() == LoongArch::R0; in isTerminator()
128 case LoongArch::JIRL: in isCall()
129 return Inst.getOperand(0).getReg() != LoongArch::R0; in isCall()
140 case LoongArch::JIRL: in isReturn()
141 return Inst.getOperand(0).getReg() == LoongArch::R0 && in isReturn()
142 Inst.getOperand(1).getReg() == LoongArch::R1; in isReturn()
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H A DLoongArchELFObjectWriter.cpp1 //===-- LoongArchELFObjectWriter.cpp - LoongArch ELF Writer ---*- C++ -*---===//
71 case LoongArch::fixup_loongarch_b16: in getRelocType()
73 case LoongArch::fixup_loongarch_b21: in getRelocType()
75 case LoongArch::fixup_loongarch_b26: in getRelocType()
77 case LoongArch::fixup_loongarch_abs_hi20: in getRelocType()
79 case LoongArch::fixup_loongarch_abs_lo12: in getRelocType()
81 case LoongArch::fixup_loongarch_abs64_lo20: in getRelocType()
83 case LoongArch::fixup_loongarch_abs64_hi12: in getRelocType()
85 case LoongArch::fixup_loongarch_tls_le_hi20: in getRelocType()
87 case LoongArch in getRelocType()
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H A DLoongArchMatInt.cpp30 Insts.push_back(Inst(LoongArch::LU52I_D, SignExtend64<12>(Highest12))); in generateInstSeq()
35 Insts.push_back(Inst(LoongArch::ORI, Lo12)); in generateInstSeq()
37 Insts.push_back(Inst(LoongArch::ADDI_W, SignExtend64<12>(Lo12))); in generateInstSeq()
39 Insts.push_back(Inst(LoongArch::LU12I_W, SignExtend64<20>(Hi20))); in generateInstSeq()
41 Insts.push_back(Inst(LoongArch::ORI, Lo12)); in generateInstSeq()
45 Insts.push_back(Inst(LoongArch::LU32I_D, SignExtend64<20>(Higher20))); in generateInstSeq()
48 Insts.push_back(Inst(LoongArch::LU52I_D, SignExtend64<12>(Highest12))); in generateInstSeq()
H A DLoongArchBaseInfo.cpp85 return !Is64Bit && FeatureBits[LoongArch::FeatureBasicF]; in computeTargetABI()
87 return !Is64Bit && FeatureBits[LoongArch::FeatureBasicD]; in computeTargetABI()
91 return Is64Bit && FeatureBits[LoongArch::FeatureBasicF]; in computeTargetABI()
93 return Is64Bit && FeatureBits[LoongArch::FeatureBasicD]; in computeTargetABI()
161 if (FeatureBits[LoongArch::FeatureBasicD]) in computeTargetABI()
163 if (FeatureBits[LoongArch::FeatureBasicF]) in computeTargetABI()
191 MCRegister getBPReg() { return LoongArch::R31; } in getBPReg()
H A DLoongArchAsmBackend.cpp68 static_assert((std::size(Infos)) == LoongArch::NumTargetFixupKinds, in getFixupKindInfo()
100 case LoongArch::fixup_loongarch_b16: { in adjustFixupValue()
107 case LoongArch::fixup_loongarch_b21: { in adjustFixupValue()
114 case LoongArch::fixup_loongarch_b26: { in adjustFixupValue()
121 case LoongArch::fixup_loongarch_abs_hi20: in adjustFixupValue()
122 case LoongArch::fixup_loongarch_tls_le_hi20: in adjustFixupValue()
124 case LoongArch::fixup_loongarch_abs_lo12: in adjustFixupValue()
125 case LoongArch::fixup_loongarch_tls_le_lo12: in adjustFixupValue()
127 case LoongArch::fixup_loongarch_abs64_lo20: in adjustFixupValue()
128 case LoongArch::fixup_loongarch_tls_le64_lo20: in adjustFixupValue()
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H A DLoongArchFixupKinds.h15 #undef LoongArch
18 namespace LoongArch {
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp34 bool is64Bit() const { return getSTI().hasFeature(LoongArch::Feature64Bit); } in is64Bit()
197 LoongArchMCRegisterClasses[LoongArch::GPRRegClassID].contains( in isGPR()
606 assert(Reg >= LoongArch::F0 && Reg <= LoongArch::F31 && "Invalid register"); in convertFPR32ToFPR64()
607 return Reg - LoongArch::F0 + LoongArch::F0_64; in convertFPR32ToFPR64()
617 assert(!(RegNo >= LoongArch::F0_64 && RegNo <= LoongArch::F31_64)); in matchRegisterNameHelper()
619 static_assert(LoongArch::F0 < LoongArch::F0_64, in matchRegisterNameHelper()
621 if (RegNo == LoongArch::NoRegister) in matchRegisterNameHelper()
624 return RegNo == LoongArch::NoRegister; in matchRegisterNameHelper()
662 if (RegNo == LoongArch::NoRegister) in parseRegister()
838 case LoongArch::PCALAU12I: in emitLAInstSeq()
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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DLoongArchTargetParser.cpp17 using namespace llvm::LoongArch;
26 {NAME, LoongArch::ArchKind::KIND, FEATURES},
30 bool LoongArch::isValidArchName(StringRef Arch) { in isValidArchName()
37 bool LoongArch::getArchFeatures(StringRef Arch, in getArchFeatures()
61 bool LoongArch::isValidCPUName(StringRef Name) { return isValidArchName(Name); } in isValidCPUName()
63 void LoongArch::fillValidCPUList(SmallVectorImpl<StringRef> &Values) { in fillValidCPUList()
68 StringRef LoongArch::getDefaultArch(bool Is64Bit) { in getDefaultArch()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/Disassembler/
H A DLoongArchDisassembler.cpp63 Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo)); in DecodeGPRRegisterClass()
72 Inst.addOperand(MCOperand::createReg(LoongArch::F0 + RegNo)); in DecodeFPR32RegisterClass()
81 Inst.addOperand(MCOperand::createReg(LoongArch::F0_64 + RegNo)); in DecodeFPR64RegisterClass()
90 Inst.addOperand(MCOperand::createReg(LoongArch::FCC0 + RegNo)); in DecodeCFRRegisterClass()
99 Inst.addOperand(MCOperand::createReg(LoongArch::FCSR0 + RegNo)); in DecodeFCSRRegisterClass()
108 Inst.addOperand(MCOperand::createReg(LoongArch::VR0 + RegNo)); in DecodeLSX128RegisterClass()
117 Inst.addOperand(MCOperand::createReg(LoongArch::XR0 + RegNo)); in DecodeLASX256RegisterClass()
126 Inst.addOperand(MCOperand::createReg(LoongArch::SCR0 + RegNo)); in DecodeSCRRegisterClass()
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DLoongArch.cpp25 class LoongArch final : public TargetInfo { class
27 LoongArch();
173 LoongArch::LoongArch() { in LoongArch() function in LoongArch
229 uint32_t LoongArch::calcEFlags() const { in calcEFlags()
279 int64_t LoongArch::getImplicitAddend(const uint8_t *buf, RelType type) const { in getImplicitAddend()
309 void LoongArch::writeGotPlt(uint8_t *buf, const Symbol &s) const { in writeGotPlt()
316 void LoongArch::writeIgotPlt(uint8_t *buf, const Symbol &s) const { in writeIgotPlt()
325 void LoongArch::writePltHeader(uint8_t *buf) const { in writePltHeader()
359 void LoongArch::writePlt(uint8_t *buf, const Symbol &sym, in writePlt()
376 RelType LoongArch::getDynRel(RelType type) const { in getDynRel()
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/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ELFRelocs/
H A DLoongArch.def5 // These types and values are from the LoongArch ELF psABI which can be found at
6 // https://github.com/loongson/LoongArch-Documentation
66 // Spec addition: https://github.com/loongson/LoongArch-Documentation/pull/57
107 // Relocs added in ELF for the LoongArch™ Architecture v20230519, part of the
108 // v2.10 LoongArch ABI specs.
124 // Relocs added in ELF for the LoongArch™ Architecture v20231102, part of the
125 // v2.20 LoongArch ABI specs.
130 // Relocs added in ELF for the LoongArch™ Architecture v20231219, part of the
131 // v2.30 LoongArch ABI specs.

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