| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 1033 struct LogicOp { struct
1034 LogicOp() = default;
1035 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize) in LogicOp() argument
1047 static LogicOp interpretAndImmediate(unsigned Opcode) { in interpretAndImmediate()
1049 case SystemZ::NILMux: return LogicOp(32, 0, 16); in interpretAndImmediate()
1050 case SystemZ::NIHMux: return LogicOp(32, 16, 16); in interpretAndImmediate()
1051 case SystemZ::NILL64: return LogicOp(64, 0, 16); in interpretAndImmediate()
1052 case SystemZ::NILH64: return LogicOp(64, 16, 16); in interpretAndImmediate()
1053 case SystemZ::NIHL64: return LogicOp(64, 32, 16); in interpretAndImmediate()
1054 case SystemZ::NIHH64: return LogicOp(64, 48, 16); in interpretAndImmediate()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 2907 SDValue computeLogicOpInGPR(SDValue LogicOp);
3078 SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) { in computeLogicOpInGPR() argument
3079 assert(ISD::isBitwiseLogicOp(LogicOp.getOpcode()) && in computeLogicOpInGPR()
3081 assert(LogicOp.getValueType() == MVT::i1 && in computeLogicOpInGPR()
3083 SDLoc dl(LogicOp); in computeLogicOpInGPR()
3087 bool IsBitwiseNegation = isBitwiseNot(LogicOp); in computeLogicOpInGPR()
3108 LHS = getLogicOperand(LogicOp.getOperand(0)); in computeLogicOpInGPR()
3109 RHS = getLogicOperand(LogicOp.getOperand(1)); in computeLogicOpInGPR()
3126 switch (LogicOp.getOpcode()) { in computeLogicOpInGPR()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6151 static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) { in foldAndOrOfSETCC() argument
6154 (LogicOp->getOpcode() == ISD::AND || LogicOp->getOpcode() == ISD::OR) && in foldAndOrOfSETCC()
6158 SDValue LHS = LogicOp->getOperand(0); in foldAndOrOfSETCC()
6159 SDValue RHS = LogicOp->getOperand(1); in foldAndOrOfSETCC()
6166 LogicOp, LHS.getNode(), RHS.getNode()); in foldAndOrOfSETCC()
6178 EVT VT = LogicOp->getValueType(0); in foldAndOrOfSETCC()
6180 SDLoc DL(LogicOp); in foldAndOrOfSETCC()
6249 bool IsOr = (LogicOp->getOpcode() == ISD::OR); in foldAndOrOfSETCC()
6256 getMinMaxOpcodeForFP(Operand1, Operand2, CC, LogicOp->getOpcode(), in foldAndOrOfSETCC()
6271 CCL == (LogicOp->getOpcode() == ISD::AND ? ISD::SETNE : ISD::SETEQ) && in foldAndOrOfSETCC()
[all …]
|
| H A D | TargetLowering.cpp | 4523 unsigned LogicOp = Cond == ISD::SETEQ ? ISD::OR : ISD::AND; in SimplifySetCC() local
4524 return DAG.getNode(LogicOp, dl, VT, IsXZero, IsYZero); in SimplifySetCC()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1083 isDesirableToCombineLogicOpOfSETCC(const SDNode *LogicOp,
|
| H A D | X86ISelLowering.cpp | 21876 unsigned LogicOp = IsFABS ? X86ISD::FAND : in LowerFABSorFNEG() local
21882 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask); in LowerFABSorFNEG()
21887 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask); in LowerFABSorFNEG()
22475 ISD::NodeType LogicOp = CmpNull ? ISD::OR : ISD::AND; in MatchVectorAllEqualTest() local
22480 if (Op.getOpcode() == LogicOp && matchScalarReduction(Op, LogicOp, VecIns)) { in MatchVectorAllEqualTest()
22498 VecIns.push_back(DAG.getNode(LogicOp, DL, VT, LHS, RHS)); in MatchVectorAllEqualTest()
22512 DAG.matchBinOpReduction(Op.getNode(), BinOp, {LogicOp})) { in MatchVectorAllEqualTest()
58021 const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const { in isDesirableToCombineLogicOpOfSETCC() argument
58023 EVT VT = LogicOp->getValueType(0); in isDesirableToCombineLogicOpOfSETCC()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 8756 Instruction *LogicOp; in splitBranchCondition() local
8759 m_Br(m_OneUse(m_Instruction(LogicOp)), TBB, FBB))) in splitBranchCondition()
8772 if (match(LogicOp, in splitBranchCondition()
8775 else if (match(LogicOp, m_LogicalOr(m_OneUse(m_Value(Cond1)), in splitBranchCondition()
8802 LogicOp->eraseFromParent(); in splitBranchCondition()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 4330 const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const { in isDesirableToCombineLogicOpOfSETCC() argument
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 10294 unsigned LogicOp = (Cond == ISD::SETEQ) ? ISD::AND : ISD::OR; in performOrXorChainCombine() local
10299 Cmp = DAG.getNode(LogicOp, DL, VT, Cmp, CmpChain); in performOrXorChainCombine()
|