| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 1064 struct LogicOp { struct
1065 LogicOp() = default;
1066 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize) in LogicOp() argument
1078 static LogicOp interpretAndImmediate(unsigned Opcode) { in interpretAndImmediate()
1080 case SystemZ::NILMux: return LogicOp(32, 0, 16); in interpretAndImmediate()
1081 case SystemZ::NIHMux: return LogicOp(32, 16, 16); in interpretAndImmediate()
1082 case SystemZ::NILL64: return LogicOp(64, 0, 16); in interpretAndImmediate()
1083 case SystemZ::NILH64: return LogicOp(64, 16, 16); in interpretAndImmediate()
1084 case SystemZ::NIHL64: return LogicOp(64, 32, 16); in interpretAndImmediate()
1085 case SystemZ::NIHH64: return LogicOp(64, 48, 16); in interpretAndImmediate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 2907 SDValue computeLogicOpInGPR(SDValue LogicOp);
3077 SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) { in computeLogicOpInGPR() argument
3078 assert(ISD::isBitwiseLogicOp(LogicOp.getOpcode()) && in computeLogicOpInGPR()
3080 assert(LogicOp.getValueType() == MVT::i1 && in computeLogicOpInGPR()
3082 SDLoc dl(LogicOp); in computeLogicOpInGPR()
3086 bool IsBitwiseNegation = isBitwiseNot(LogicOp); in computeLogicOpInGPR()
3107 LHS = getLogicOperand(LogicOp.getOperand(0)); in computeLogicOpInGPR()
3108 RHS = getLogicOperand(LogicOp.getOperand(1)); in computeLogicOpInGPR()
3125 switch (LogicOp.getOpcode()) { in computeLogicOpInGPR()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6530 static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) { in foldAndOrOfSETCC() argument
6533 (LogicOp->getOpcode() == ISD::AND || LogicOp->getOpcode() == ISD::OR) && in foldAndOrOfSETCC()
6537 SDValue LHS = LogicOp->getOperand(0); in foldAndOrOfSETCC()
6538 SDValue RHS = LogicOp->getOperand(1); in foldAndOrOfSETCC()
6545 LogicOp, LHS.getNode(), RHS.getNode()); in foldAndOrOfSETCC()
6557 EVT VT = LogicOp->getValueType(0); in foldAndOrOfSETCC()
6559 SDLoc DL(LogicOp); in foldAndOrOfSETCC()
6628 bool IsOr = (LogicOp->getOpcode() == ISD::OR); in foldAndOrOfSETCC()
6635 getMinMaxOpcodeForFP(Operand1, Operand2, CC, LogicOp->getOpcode(), in foldAndOrOfSETCC()
6648 ((LogicOp->getOpcode() == ISD::AND && CCL == ISD::SETO) || in foldAndOrOfSETCC()
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| H A D | TargetLowering.cpp | 4736 unsigned LogicOp = Cond == ISD::SETEQ ? ISD::OR : ISD::AND; in SimplifySetCC() local
4737 return DAG.getNode(LogicOp, dl, VT, IsXZero, IsYZero); in SimplifySetCC()
9023 unsigned LogicOp = IsInvertedFP ? ISD::OR : ISD::AND; in expandIS_FPCLASS() local
9024 return DAG.getNode(LogicOp, DL, ResultVT, IsFinite, IsNormal); in expandIS_FPCLASS()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1169 isDesirableToCombineLogicOpOfSETCC(const SDNode *LogicOp,
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| H A D | X86ISelLowering.cpp | 22611 unsigned LogicOp = IsFABS ? X86ISD::FAND : in LowerFABSorFNEG() local
22617 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask); in LowerFABSorFNEG()
22622 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask); in LowerFABSorFNEG()
23211 ISD::NodeType LogicOp = CmpNull ? ISD::OR : ISD::AND; in MatchVectorAllEqualTest() local
23216 if (Op.getOpcode() == LogicOp && matchScalarReduction(Op, LogicOp, VecIns)) { in MatchVectorAllEqualTest()
23234 VecIns.push_back(DAG.getNode(LogicOp, DL, VT, LHS, RHS)); in MatchVectorAllEqualTest()
23248 DAG.matchBinOpReduction(Op.getNode(), BinOp, {LogicOp})) { in MatchVectorAllEqualTest()
53404 SDValue LogicOp = DAG.getNode( in combineStore() local
53407 return DAG.getStore(St->getChain(), dl, LogicOp, St->getBasePtr(), in combineStore()
60772 const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const { in isDesirableToCombineLogicOpOfSETCC() argument
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 9156 Instruction *LogicOp; in splitBranchCondition() local
9159 m_Br(m_OneUse(m_Instruction(LogicOp)), TBB, FBB))) in splitBranchCondition()
9172 if (match(LogicOp, in splitBranchCondition()
9175 else if (match(LogicOp, m_LogicalOr(m_OneUse(m_Value(Cond1)), in splitBranchCondition()
9202 LogicOp->eraseFromParent(); in splitBranchCondition()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 4505 const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const { in isDesirableToCombineLogicOpOfSETCC() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 10980 unsigned LogicOp = (Cond == ISD::SETEQ) ? ISD::AND : ISD::OR; in performOrXorChainCombine() local
10985 Cmp = DAG.getNode(LogicOp, DL, VT, Cmp, CmpChain); in performOrXorChainCombine()
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