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Searched refs:LoadedVT (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1592 EVT LoadedVT = LD->getMemoryVT(); in tryARMIndexedLoad() local
1597 if (LoadedVT == MVT::i32 && isPre && in tryARMIndexedLoad()
1601 } else if (LoadedVT == MVT::i32 && !isPre && in tryARMIndexedLoad()
1605 } else if (LoadedVT == MVT::i32 && in tryARMIndexedLoad()
1610 } else if (LoadedVT == MVT::i16 && in tryARMIndexedLoad()
1616 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) { in tryARMIndexedLoad()
1667 EVT LoadedVT = LD->getMemoryVT(); in tryT1IndexedLoad() local
1670 LoadedVT.getSimpleVT().SimpleTy != MVT::i32) in tryT1IndexedLoad()
1698 EVT LoadedVT = LD->getMemoryVT(); in tryT2IndexedLoad() local
1705 switch (LoadedVT.getSimpleVT().SimpleTy) { in tryT2IndexedLoad()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp81 EVT LoadedVT = LD->getMemoryVT(); in INITIALIZE_PASS() local
88 bool IsValidInc = HII->isValidAutoIncImm(LoadedVT, Inc); in INITIALIZE_PASS()
90 assert(LoadedVT.isSimple()); in INITIALIZE_PASS()
91 switch (LoadedVT.getSimpleVT().SimpleTy) { in INITIALIZE_PASS()
162 assert(LoadedVT.getSizeInBits() <= 32); in INITIALIZE_PASS()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp1025 const MVT LoadedVT = LoadedEVT.getSimpleVT(); in tryLoad() local
1036 const unsigned FromTypeWidth = LoadedVT.getSizeInBits(); in tryLoad()
1176 const MVT LoadedVT = LoadedEVT.getSimpleVT(); in tryLDG() local
1180 const unsigned TotalWidth = LoadedVT.getSizeInBits(); in tryLDG()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp5566 EVT LoadedVT = LD->getMemoryVT(); in Select() local
5586 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5587 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5598 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5599 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5623 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5624 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5635 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && in Select()
5637 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp301 EVT LoadedVT = LD->getMemoryVT(); in LegalizeOp() local
302 if (LoadedVT.isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
303 Action = TLI.getLoadExtAction(ExtType, LD->getValueType(0), LoadedVT); in LegalizeOp()
H A DTargetLowering.cpp10284 EVT LoadedVT = LD->getMemoryVT(); in expandUnalignedLoad() local
10289 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); in expandUnalignedLoad()
10290 if (isTypeLegal(intVT) && isTypeLegal(LoadedVT)) { in expandUnalignedLoad()
10292 LoadedVT.isVector()) { in expandUnalignedLoad()
10301 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); in expandUnalignedLoad()
10302 if (LoadedVT != VT) in expandUnalignedLoad()
10312 unsigned LoadedBytes = LoadedVT.getStoreSize(); in expandUnalignedLoad()
10317 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
10366 LoadedVT); in expandUnalignedLoad()
10372 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && in expandUnalignedLoad()
[all …]
H A DDAGCombiner.cpp6810 EVT LoadedVT = LoadN->getMemoryVT(); in isAndLoadExtLoad() local
6812 if (ExtVT == LoadedVT && in isAndLoadExtLoad()
6826 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound()) in isAndLoadExtLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp15758 EVT LoadedVT = ALoad->getMemoryVT(); in reduceANDOfAtomicLoad() local
15763 uint64_t ExpectedMask = maskTrailingOnes<uint64_t>(LoadedVT.getSizeInBits()); in reduceANDOfAtomicLoad()