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Searched refs:LoadVT (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp6241 static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT, in adjustLoadValueTypeImpl() argument
6244 if (!LoadVT.isVector()) in adjustLoadValueTypeImpl()
6250 EVT FittingLoadVT = LoadVT; in adjustLoadValueTypeImpl()
6251 if ((LoadVT.getVectorNumElements() % 2) == 1) { in adjustLoadValueTypeImpl()
6253 EVT::getVectorVT(*DAG.getContext(), LoadVT.getVectorElementType(), in adjustLoadValueTypeImpl()
6254 LoadVT.getVectorNumElements() + 1); in adjustLoadValueTypeImpl()
6269 if ((LoadVT.getVectorNumElements() % 2) == 1) in adjustLoadValueTypeImpl()
6289 EVT LoadVT = M->getValueType(0); in adjustLoadValueType() local
6291 EVT EquivLoadVT = LoadVT; in adjustLoadValueType()
6292 if (LoadVT.isVector()) { in adjustLoadValueType()
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H A DSIISelLowering.h286 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp837 EVT LoadVT = Ld->getMemoryVT(); in tryIndexedLoad() local
857 if (LoadVT == MVT::i8 && IsPre) in tryIndexedLoad()
859 else if (LoadVT == MVT::i8 && IsPost) in tryIndexedLoad()
861 else if (LoadVT == MVT::i16 && IsPre) in tryIndexedLoad()
863 else if (LoadVT == MVT::i16 && IsPost) in tryIndexedLoad()
865 else if (LoadVT == MVT::i32 && IsPre) in tryIndexedLoad()
867 else if (LoadVT == MVT::i32 && IsPost) in tryIndexedLoad()
869 else if (LoadVT == MVT::i64 && IsPre) in tryIndexedLoad()
871 else if (LoadVT == MVT::i64 && IsPost) in tryIndexedLoad()
H A DRISCVISelLowering.cpp17811 EVT LoadVT = VPLoad->getValueType(0); in performVP_REVERSECombine() local
17814 if (!LoadVT.getVectorElementType().isByteSized() || in performVP_REVERSECombine()
17855 LoadVT, DL, VPLoad->getChain(), Base, Stride, LoadMask, in performVP_REVERSECombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp2300 EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, in isLoadBitCastBeneficial() argument
2304 if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() && in isLoadBitCastBeneficial()
2310 if (!LoadVT.isSimple() || !BitcastVT.isSimple()) in isLoadBitCastBeneficial()
2313 MVT LoadMVT = LoadVT.getSimpleVT(); in isLoadBitCastBeneficial()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DStatepointLowering.cpp1279 auto LoadVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitGCRelocate() local
1283 DAG.getLoad(LoadVT, getCurSDLoc(), Chain, SpillSlot, LoadMMO); in visitGCRelocate()
H A DSelectionDAGBuilder.cpp9006 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, in getMemCmpLoad() argument
9013 Type::getIntNTy(PtrVal->getContext(), LoadVT.getScalarSizeInBits()); in getMemCmpLoad()
9014 if (LoadVT.isVector()) in getMemCmpLoad()
9015 LoadTy = FixedVectorType::get(LoadTy, LoadVT.getVectorNumElements()); in getMemCmpLoad()
9038 Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, Ptr, in getMemCmpLoad()
9113 MVT LoadVT; in visitMemCmpBCmpCall() local
9119 LoadVT = MVT::i16; in visitMemCmpBCmpCall()
9122 LoadVT = MVT::i32; in visitMemCmpBCmpCall()
9127 LoadVT = hasFastLoadsAndCompare(NumBitsToCompare); in visitMemCmpBCmpCall()
9131 if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE) in visitMemCmpBCmpCall()
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H A DLegalizeIntegerTypes.cpp4812 EVT LoadVT = VT; in ExpandIntRes_ShiftThroughStack() local
4814 LoadVT = TLI.getTypeToTransformTo(*DAG.getContext(), LoadVT); in ExpandIntRes_ShiftThroughStack()
4815 } while (!TLI.isTypeLegal(LoadVT)); in ExpandIntRes_ShiftThroughStack()
4817 const unsigned ShiftUnitInBits = LoadVT.getStoreSizeInBits(); in ExpandIntRes_ShiftThroughStack()
4911 commonAlignment(StackAlign, LoadVT.getStoreSize())); in ExpandIntRes_ShiftThroughStack()
H A DLegalizeDAG.cpp890 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT()); in LegalizeLoadOps() local
891 if ((LoadVT.isFloatingPoint() == SrcVT.isFloatingPoint()) && in LegalizeLoadOps()
893 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT))) { in LegalizeLoadOps()
897 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType; in LegalizeLoadOps()
899 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr, in LegalizeLoadOps()
H A DTargetLowering.cpp10139 EVT LoadVT = EVT::getIntegerVT(*DAG.getContext(), NumLoadBits); in scalarizeVectorLoad() local
10146 APInt::getLowBitsSet(NumLoadBits, SrcEltBits), SL, LoadVT); in scalarizeVectorLoad()
10151 DAG.getExtLoad(ISD::EXTLOAD, SL, LoadVT, Chain, BasePTR, in scalarizeVectorLoad()
10160 ShiftIntoIdx * SrcEltVT.getSizeInBits(), LoadVT, SL); in scalarizeVectorLoad()
10161 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount); in scalarizeVectorLoad()
10163 DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask); in scalarizeVectorLoad()
H A DDAGCombiner.cpp7403 EVT LoadVT = MLoad->getMemoryVT(); in visitAND() local
7405 if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT, LoadVT)) { in visitAND()
7410 LoadVT.getVectorElementType().getScalarSizeInBits(); in visitAND()
7415 LoadVT, MLoad->getMemOperand(), MLoad->getAddressingMode(), in visitAND()
21413 EVT LoadVT; in getStoreMergeCandidates() local
21417 LoadVT = Ld->getMemoryVT(); in getStoreMergeCandidates()
21419 if (MemVT != LoadVT) in getStoreMergeCandidates()
21453 if (LoadVT != OtherLd->getMemoryVT()) in getStoreMergeCandidates()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h685 virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
3103 EVT LoadVT = getValueType(DL, Load->getType()); in isExtLoad() local
3107 if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) && in isExtLoad()
3120 return isLoadExtLegal(LType, VT, LoadVT); in isExtLoad()
H A DBasicTTIImpl.h1235 EVT LoadVT = EVT::getEVT(Src);
1239 TLI->isLoadExtLegal(LType, ExtVT, LoadVT))
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp3438 const EVT LoadVT = VTs[I] == MVT::i1 ? MVT::i8 : VTs[I]; in LowerFormalArguments() local
3442 LoadVT.isVector() ? LoadVT.getVectorNumElements() : 1; in LowerFormalArguments()
3446 ? LoadVT in LowerFormalArguments()
3447 : EVT::getVectorVT(F->getContext(), LoadVT.getScalarType(), in LowerFormalArguments()
3465 : DAG.getNode(LoadVT.isVector() ? ISD::EXTRACT_SUBVECTOR in LowerFormalArguments()
3467 dl, LoadVT, P, in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1563 bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
H A DX86ISelLowering.cpp3440 bool X86TargetLowering::isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, in isLoadBitCastBeneficial() argument
3443 if (!Subtarget.hasAVX512() && !LoadVT.isVector() && BitcastVT.isVector() && in isLoadBitCastBeneficial()
3447 if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1 && LoadVT == MVT::i8) in isLoadBitCastBeneficial()
3451 if (LoadVT.isVector() && BitcastVT.isVector() && in isLoadBitCastBeneficial()
3452 isTypeLegal(LoadVT) && isTypeLegal(BitcastVT)) in isLoadBitCastBeneficial()
3455 return TargetLowering::isLoadBitCastBeneficial(LoadVT, BitcastVT, DAG, MMO); in isLoadBitCastBeneficial()
45789 MVT LoadVT = VT.isFloatingPoint() ? MVT::getFloatingPointVT(SrcVTSize) in combineBitcast() local
45791 LoadVT = MVT::getVectorVT(LoadVT, SrcVT.getVectorNumElements()); in combineBitcast()
45793 SDVTList Tys = DAG.getVTList(LoadVT, MVT::Other); in combineBitcast()
55242 MVT LoadVT = MVT::getVectorVT(MemVT, 128 / NumBits); in combineX86INT_TO_FP() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp21426 EVT LoadVT = EVT::getVectorVT( in performExtBinopLoadFold() local
21429 EVT DLoadVT = LoadVT.getDoubleNumVectorElementsVT(*DAG.getContext()); in performExtBinopLoadFold()
22727 EVT LoadVT = VT; in performLDNT1Combine() local
22729 LoadVT = VT.changeTypeToInteger(); in performLDNT1Combine()
22732 SDValue PassThru = DAG.getConstant(0, DL, LoadVT); in performLDNT1Combine()
22733 SDValue L = DAG.getMaskedLoad(LoadVT, DL, MINode->getChain(), in performLDNT1Combine()
22755 EVT LoadVT = VT; in performLD1ReplicateCombine() local
22757 LoadVT = VT.changeTypeToInteger(); in performLD1ReplicateCombine()
22760 SDValue Load = DAG.getNode(Opcode, DL, {LoadVT, MVT::Other}, Ops); in performLD1ReplicateCombine()
28828 EVT LoadVT = ContainerVT; in LowerFixedLengthVectorLoadToSVE() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp8574 EVT LoadVT = N->getValueType(0); in combineBSWAP() local
8575 if (LoadVT == MVT::i16) in combineBSWAP()
8576 LoadVT = MVT::i32; in combineBSWAP()
8579 DAG.getVTList(LoadVT, MVT::Other), in combineBSWAP()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp16163 EVT LoadVT = isLaneOp ? VecTy.getVectorElementType() : AlignedVecTy; in TryCombineBaseUpdate() local
16164 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, dl, SDTys, Ops, LoadVT, in TryCombineBaseUpdate()
18925 EVT LoadVT = N->getOperand(0).getValueType().getHalfNumVectorElementsVT( in PerformMVEExtCombine() local
18928 LoadVT = LoadVT.getHalfNumVectorElementsVT(*DAG.getContext()); in PerformMVEExtCombine()
18944 VT, Chain, Ptr, MPI, LoadVT, Align(4)); in PerformMVEExtCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16842 MVT LoadVT = VT.getSimpleVT(); in PerformDAGCombine() local
16844 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 || in PerformDAGCombine()
16845 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32)) in PerformDAGCombine()