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Searched refs:LoadVT (Results 1 – 18 of 18) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp5894 static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT, in adjustLoadValueTypeImpl() argument
5897 if (!LoadVT.isVector()) in adjustLoadValueTypeImpl()
5903 EVT FittingLoadVT = LoadVT; in adjustLoadValueTypeImpl()
5904 if ((LoadVT.getVectorNumElements() % 2) == 1) { in adjustLoadValueTypeImpl()
5906 EVT::getVectorVT(*DAG.getContext(), LoadVT.getVectorElementType(), in adjustLoadValueTypeImpl()
5907 LoadVT.getVectorNumElements() + 1); in adjustLoadValueTypeImpl()
5922 if ((LoadVT.getVectorNumElements() % 2) == 1) in adjustLoadValueTypeImpl()
5943 EVT LoadVT = M->getValueType(0); in adjustLoadValueType() local
5945 EVT EquivLoadVT = LoadVT; in adjustLoadValueType()
5946 if (LoadVT.isVector()) { in adjustLoadValueType()
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H A DSIISelLowering.h274 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp763 EVT LoadVT = Ld->getMemoryVT(); in tryIndexedLoad() local
783 if (LoadVT == MVT::i8 && IsPre) in tryIndexedLoad()
785 else if (LoadVT == MVT::i8 && IsPost) in tryIndexedLoad()
787 else if (LoadVT == MVT::i16 && IsPre) in tryIndexedLoad()
789 else if (LoadVT == MVT::i16 && IsPost) in tryIndexedLoad()
791 else if (LoadVT == MVT::i32 && IsPre) in tryIndexedLoad()
793 else if (LoadVT == MVT::i32 && IsPost) in tryIndexedLoad()
795 else if (LoadVT == MVT::i64 && IsPre) in tryIndexedLoad()
797 else if (LoadVT == MVT::i64 && IsPost) in tryIndexedLoad()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp2193 EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, in isLoadBitCastBeneficial() argument
2197 if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() && in isLoadBitCastBeneficial()
2203 if (!LoadVT.isSimple() || !BitcastVT.isSimple()) in isLoadBitCastBeneficial()
2206 MVT LoadMVT = LoadVT.getSimpleVT(); in isLoadBitCastBeneficial()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DStatepointLowering.cpp1275 auto LoadVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitGCRelocate() local
1279 DAG.getLoad(LoadVT, getCurSDLoc(), Chain, SpillSlot, LoadMMO); in visitGCRelocate()
H A DSelectionDAGBuilder.cpp8853 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, in getMemCmpLoad() argument
8860 Type::getIntNTy(PtrVal->getContext(), LoadVT.getScalarSizeInBits()); in getMemCmpLoad()
8861 if (LoadVT.isVector()) in getMemCmpLoad()
8862 LoadTy = FixedVectorType::get(LoadTy, LoadVT.getVectorNumElements()); in getMemCmpLoad()
8889 Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, Ptr, in getMemCmpLoad()
8964 MVT LoadVT; in visitMemCmpBCmpCall() local
8970 LoadVT = MVT::i16; in visitMemCmpBCmpCall()
8973 LoadVT = MVT::i32; in visitMemCmpBCmpCall()
8978 LoadVT = hasFastLoadsAndCompare(NumBitsToCompare); in visitMemCmpBCmpCall()
8982 if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE) in visitMemCmpBCmpCall()
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H A DLegalizeDAG.cpp873 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT()); in LegalizeLoadOps() local
874 if ((LoadVT.isFloatingPoint() == SrcVT.isFloatingPoint()) && in LegalizeLoadOps()
876 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT))) { in LegalizeLoadOps()
880 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType; in LegalizeLoadOps()
882 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr, in LegalizeLoadOps()
H A DTargetLowering.cpp9644 EVT LoadVT = EVT::getIntegerVT(*DAG.getContext(), NumLoadBits); in scalarizeVectorLoad() local
9651 APInt::getLowBitsSet(NumLoadBits, SrcEltBits), SL, LoadVT); in scalarizeVectorLoad()
9656 DAG.getExtLoad(ISD::EXTLOAD, SL, LoadVT, Chain, BasePTR, in scalarizeVectorLoad()
9665 ShiftIntoIdx * SrcEltVT.getSizeInBits(), LoadVT, SL); in scalarizeVectorLoad()
9666 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount); in scalarizeVectorLoad()
9668 DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask); in scalarizeVectorLoad()
H A DDAGCombiner.cpp6981 EVT LoadVT = MLoad->getMemoryVT(); in visitAND() local
6983 if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT, LoadVT)) { in visitAND()
6988 LoadVT.getVectorElementType().getScalarSizeInBits(); in visitAND()
6993 LoadVT, MLoad->getMemOperand(), MLoad->getAddressingMode(), in visitAND()
20399 EVT LoadVT; in getStoreMergeCandidates() local
20403 LoadVT = Ld->getMemoryVT(); in getStoreMergeCandidates()
20405 if (MemVT != LoadVT) in getStoreMergeCandidates()
20439 if (LoadVT != OtherLd->getMemoryVT()) in getStoreMergeCandidates()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h655 virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
3018 EVT LoadVT = getValueType(DL, Load->getType()); in isExtLoad() local
3022 if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) && in isExtLoad()
3035 return isLoadExtLegal(LType, VT, LoadVT); in isExtLoad()
H A DBasicTTIImpl.h1102 EVT LoadVT = EVT::getEVT(Src);
1106 TLI->isLoadExtLegal(LType, ExtVT, LoadVT))
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp3273 EVT LoadVT = EltVT; in LowerFormalArguments() local
3275 LoadVT = MVT::i8; in LowerFormalArguments()
3280 LoadVT = MVT::i32; in LowerFormalArguments()
3282 EVT VecVT = EVT::getVectorVT(F->getContext(), LoadVT, NumElts); in LowerFormalArguments()
3305 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P, in LowerFormalArguments()
3311 else if (EltVT != LoadVT) in LowerFormalArguments()
3324 LoadVT.getFixedSizeInBits()) { in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1476 bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
H A DX86ISelLowering.cpp3259 bool X86TargetLowering::isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, in isLoadBitCastBeneficial() argument
3262 if (!Subtarget.hasAVX512() && !LoadVT.isVector() && BitcastVT.isVector() && in isLoadBitCastBeneficial()
3266 if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1 && LoadVT == MVT::i8) in isLoadBitCastBeneficial()
3270 if (LoadVT.isVector() && BitcastVT.isVector() && in isLoadBitCastBeneficial()
3271 isTypeLegal(LoadVT) && isTypeLegal(BitcastVT)) in isLoadBitCastBeneficial()
3274 return TargetLowering::isLoadBitCastBeneficial(LoadVT, BitcastVT, DAG, MMO); in isLoadBitCastBeneficial()
43956 MVT LoadVT = VT.isFloatingPoint() ? MVT::getFloatingPointVT(SrcVTSize) in combineBitcast() local
43958 LoadVT = MVT::getVectorVT(LoadVT, SrcVT.getVectorNumElements()); in combineBitcast()
43960 SDVTList Tys = DAG.getVTList(LoadVT, MVT::Other); in combineBitcast()
53409 MVT LoadVT = MVT::getVectorVT(MemVT, 128 / NumBits); in combineX86INT_TO_FP() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp20685 EVT LoadVT = EVT::getVectorVT( in performExtBinopLoadFold() local
20688 EVT DLoadVT = LoadVT.getDoubleNumVectorElementsVT(*DAG.getContext()); in performExtBinopLoadFold()
21715 EVT LoadVT = VT; in performLDNT1Combine() local
21717 LoadVT = VT.changeTypeToInteger(); in performLDNT1Combine()
21720 SDValue PassThru = DAG.getConstant(0, DL, LoadVT); in performLDNT1Combine()
21721 SDValue L = DAG.getMaskedLoad(LoadVT, DL, MINode->getChain(), in performLDNT1Combine()
21743 EVT LoadVT = VT; in performLD1ReplicateCombine() local
21745 LoadVT = VT.changeTypeToInteger(); in performLD1ReplicateCombine()
21748 SDValue Load = DAG.getNode(Opcode, DL, {LoadVT, MVT::Other}, Ops); in performLD1ReplicateCombine()
27233 EVT LoadVT = ContainerVT; in LowerFixedLengthVectorLoadToSVE() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp7485 EVT LoadVT = N->getValueType(0); in combineBSWAP() local
7486 if (LoadVT == MVT::i16) in combineBSWAP()
7487 LoadVT = MVT::i32; in combineBSWAP()
7490 DAG.getVTList(LoadVT, MVT::Other), in combineBSWAP()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15949 MVT LoadVT = VT.getSimpleVT(); in PerformDAGCombine() local
15951 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 || in PerformDAGCombine()
15952 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32)) in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp16065 EVT LoadVT = isLaneOp ? VecTy.getVectorElementType() : AlignedVecTy; in TryCombineBaseUpdate() local
16066 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, dl, SDTys, Ops, LoadVT, in TryCombineBaseUpdate()
18854 EVT LoadVT = N->getOperand(0).getValueType().getHalfNumVectorElementsVT( in PerformMVEExtCombine() local
18857 LoadVT = LoadVT.getHalfNumVectorElementsVT(*DAG.getContext()); in PerformMVEExtCombine()
18873 VT, Chain, Ptr, MPI, LoadVT, Align(4)); in PerformMVEExtCombine()