Home
last modified time | relevance | path

Searched refs:LoadReg (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPreloadKernArgProlog.cpp47 Register LoadReg = Register(); member
167 Register LoadReg = TRI.getMatchingSuperReg(KernArgPreloadSGPR, in getLoadParameters() local
169 if (LoadReg) { in getLoadParameters()
171 C.LoadReg = LoadReg; in getLoadParameters()
193 BuildMI(BackCompatMBB, DebugLoc(), TII.get(Config.Opcode), Config.LoadReg) in addBackCompatLoads()
H A DAMDGPUPostLegalizerCombiner.cpp378 Register LoadReg = MI.getOperand(1).getReg(); in matchCombineSignExtendInReg() local
379 if (!MRI.hasOneNonDBGUse(LoadReg)) in matchCombineSignExtendInReg()
384 MachineInstr *LoadMI = MRI.getVRegDef(LoadReg); in matchCombineSignExtendInReg()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DStackSlotColoring.cpp487 Register LoadReg; in RemoveDeadStores() local
491 if (!(LoadReg = TII->isLoadFromStackSlot(*I, FirstSS, LoadSize))) in RemoveDeadStores()
501 if (FirstSS != SecondSS || LoadReg != StoreReg || FirstSS == -1 || in RemoveDeadStores()
508 if (NextMI->findRegisterUseOperandIdx(LoadReg, /*TRI=*/nullptr, true) != in RemoveDeadStores()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp2296 Register LoadReg = getRegForValue(LI); in tryToFoldLoad() local
2297 if (!LoadReg) in tryToFoldLoad()
2303 if (!MRI.hasOneUse(LoadReg)) in tryToFoldLoad()
2308 if (FuncInfo.RegsWithFixups.contains(LoadReg)) in tryToFoldLoad()
2311 MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg); in tryToFoldLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp763 Register LoadReg; in handleConstantAddresses() local
765 LoadReg = I->second; in handleConstantAddresses()
790 LoadReg = createResultReg(RC); in handleConstantAddresses()
792 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), LoadReg); in handleConstantAddresses()
799 LocalValueMap[V] = LoadReg; in handleConstantAddresses()
804 AM.Base.Reg = LoadReg; in handleConstantAddresses()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp324 Register LoadReg = Load->getPointerReg(); in shouldLowerTailCallStackArg() local
325 auto *LoadAddrDef = MRI.getVRegDef(LoadReg); in shouldLowerTailCallStackArg()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp782 Register LoadReg = LoadMI->getDstReg(); in matchCombineExtendingLoads() local
784 LLT LoadValueTy = MRI.getType(LoadReg); in matchCombineExtendingLoads()
811 for (auto &UseMI : MRI.use_nodbg_instructions(LoadReg)) { in matchCombineExtendingLoads()
984 Register LoadReg = LoadMI->getDstReg(); in matchCombineLoadWithAndMask() local
985 LLT RegTy = MRI.getType(LoadReg); in matchCombineLoadWithAndMask()
1149 Register LoadReg; in applySextInRegOfLoad() local
1151 std::tie(LoadReg, ScalarSizeBits) = MatchInfo; in applySextInRegOfLoad()
1152 GLoad *LoadDef = cast<GLoad>(MRI.getVRegDef(LoadReg)); in applySextInRegOfLoad()
H A DLegalizerHelper.cpp4068 Register LoadReg = DstReg; in lowerLoad() local
4075 LoadReg = MRI.createGenericVirtualRegister(WideMemTy); in lowerLoad()
4080 MIRBuilder.buildSExtInReg(LoadReg, NewLoad, MemSizeInBits); in lowerLoad()
4085 MIRBuilder.buildAssertZExt(LoadReg, NewLoad, MemSizeInBits); in lowerLoad()
4087 MIRBuilder.buildLoad(LoadReg, PtrReg, *NewMMO); in lowerLoad()
4091 MIRBuilder.buildTrunc(DstReg, LoadReg); in lowerLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4537 Register LoadReg = MI->getOperand(1).getReg(); in optimizeIntExtLoad() local
4538 LoadMI = MRI.getUniqueVRegDef(LoadReg); in optimizeIntExtLoad()