Searched refs:LoadReg (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | StackSlotColoring.cpp | 475 unsigned LoadReg = 0; in RemoveDeadStores() local
479 if (!(LoadReg = TII->isLoadFromStackSlot(*I, FirstSS, LoadSize))) in RemoveDeadStores()
489 if (FirstSS != SecondSS || LoadReg != StoreReg || FirstSS == -1 || in RemoveDeadStores()
496 if (NextMI->findRegisterUseOperandIdx(LoadReg, /*TRI=*/nullptr, true) != in RemoveDeadStores()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPostLegalizerCombiner.cpp | 378 Register LoadReg = MI.getOperand(1).getReg(); in matchCombineSignExtendInReg() local
379 if (!MRI.hasOneNonDBGUse(LoadReg)) in matchCombineSignExtendInReg()
384 MachineInstr *LoadMI = MRI.getVRegDef(LoadReg); in matchCombineSignExtendInReg()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 2352 Register LoadReg = getRegForValue(LI); in tryToFoldLoad() local
2353 if (!LoadReg) in tryToFoldLoad()
2359 if (!MRI.hasOneUse(LoadReg)) in tryToFoldLoad()
2364 if (FuncInfo.RegsWithFixups.contains(LoadReg)) in tryToFoldLoad()
2367 MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg); in tryToFoldLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 763 Register LoadReg; in handleConstantAddresses() local
765 LoadReg = I->second; in handleConstantAddresses()
790 LoadReg = createResultReg(RC); in handleConstantAddresses()
792 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), LoadReg); in handleConstantAddresses()
799 LocalValueMap[V] = LoadReg; in handleConstantAddresses()
804 AM.Base.Reg = LoadReg; in handleConstantAddresses()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 716 Register LoadReg = LoadMI->getDstReg(); in matchCombineExtendingLoads() local
718 LLT LoadValueTy = MRI.getType(LoadReg); in matchCombineExtendingLoads()
745 for (auto &UseMI : MRI.use_nodbg_instructions(LoadReg)) { in matchCombineExtendingLoads()
919 Register LoadReg = LoadMI->getDstReg(); in matchCombineLoadWithAndMask() local
920 LLT RegTy = MRI.getType(LoadReg); in matchCombineLoadWithAndMask()
1084 Register LoadReg; in applySextInRegOfLoad() local
1086 std::tie(LoadReg, ScalarSizeBits) = MatchInfo; in applySextInRegOfLoad()
1087 GLoad *LoadDef = cast<GLoad>(MRI.getVRegDef(LoadReg)); in applySextInRegOfLoad()
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| H A D | LegalizerHelper.cpp | 3491 Register LoadReg = DstReg; in lowerLoad() local
3498 LoadReg = MRI.createGenericVirtualRegister(WideMemTy); in lowerLoad()
3503 MIRBuilder.buildSExtInReg(LoadReg, NewLoad, MemSizeInBits); in lowerLoad()
3508 MIRBuilder.buildAssertZExt(LoadReg, NewLoad, MemSizeInBits); in lowerLoad()
3510 MIRBuilder.buildLoad(LoadReg, PtrReg, *NewMMO); in lowerLoad()
3514 MIRBuilder.buildTrunc(DstReg, LoadReg); in lowerLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4534 Register LoadReg = MI->getOperand(1).getReg(); in optimizeIntExtLoad() local
4535 LoadMI = MRI.getUniqueVRegDef(LoadReg); in optimizeIntExtLoad()
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