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Searched refs:LoadOp (Results 1 – 21 of 21) sorted by relevance

/freebsd/contrib/llvm-project/clang/lib/CIR/Dialect/IR/
H A DCIRMemorySlot.cpp58 bool cir::LoadOp::loadsFrom(const MemorySlot &slot) { in loadsFrom()
62 bool cir::LoadOp::storesTo(const MemorySlot &slot) { return false; } in storesTo()
64 Value cir::LoadOp::getStored(const MemorySlot &slot, OpBuilder &builder, in getStored()
69 bool cir::LoadOp::canUsesBeRemoved( in canUsesBeRemoved()
80 DeletionKind cir::LoadOp::removeBlockingUses( in removeBlockingUses()
/freebsd/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_riscv.cpp161 const uint32_t LoadOp = PatchOpcodes::PO_LD; in patchSled() local
164 const uint32_t LoadOp = PatchOpcodes::PO_LW; in patchSled() local
201 encodeITypeInstruction(LoadOp, RegNum::RN_SP, RegNum::RN_T1, XLenBytes); in patchSled()
203 Address[Idx++] = encodeITypeInstruction(LoadOp, RegNum::RN_SP, in patchSled()
205 Address[Idx++] = encodeITypeInstruction(LoadOp, RegNum::RN_SP, in patchSled()
/freebsd/contrib/llvm-project/clang/lib/CIR/CodeGen/
H A DCIRGenCXXABI.cpp54 return cgf.getBuilder().create<cir::LoadOp>( in loadIncomingCXXThis()
H A DCIRGenBuilder.h337 cir::LoadOp createLoad(mlir::Location loc, Address addr,
340 return create<cir::LoadOp>(loc, addr.getPointer(), /*isDeref=*/false,
H A DCIRGenExprAggregate.cpp198 cir::LoadOp currentElement = builder.createLoad(loc, tmpAddr); in emitArrayInit()
H A DCIRGenExpr.cpp629 dyn_cast<cir::LoadOp>(addr.getPointer().getDefiningOp())) { in emitUnaryOpLValue()
1646 cir::LoadOp load = in emitLoadOfReference()
1647 builder.create<cir::LoadOp>(loc, refLVal.getAddress().getElementType(), in emitLoadOfReference()
H A DCIRGenFunction.cpp285 auto value = builder.create<cir::LoadOp>( in emitReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.td1089 multiclass LdPat<PatFrag LoadOp, ImmLeaf imm_type, Instruction Inst, ValueType Type> {
1090 def : Pat<(Type (LoadOp GPR:$rs1)), (Inst GPR:$rs1, 0)>;
1091 def : Pat<(Type (LoadOp (i32 frameindex:$rs1))), (Inst (i32 (to_tframeindex tframeindex:$rs1)), 0)>;
1092 def : Pat<(Type (LoadOp (add GPR:$rs1, imm_type:$uimm))),
1094 def : Pat<(Type (LoadOp (add frameindex:$rs1, imm_type:$uimm))),
1096 def : Pat<(Type (LoadOp (eqToAdd frameindex:$rs1, imm_type:$uimm))),
1098 def : Pat<(Type (LoadOp (add GPR:$rs1, tglobaladdr:$gd))),
1114 multiclass LdrPat<PatFrag LoadOp, Instruction Inst, ValueType Type> {
1115 def : Pat<(Type (LoadOp (add GPR:$rs1, GPR:$rs2))), (Inst GPR:$rs1, GPR:$rs2, 0)>;
1116 def : Pat<(Type (LoadOp (ad
[all...]
/freebsd/contrib/llvm-project/clang/lib/CIR/Lowering/DirectToLLVM/
H A DLowerToLLVM.h190 class CIRToLLVMLoadOpLowering : public mlir::OpConversionPattern<cir::LoadOp> {
200 matchAndRewrite(cir::LoadOp op, OpAdaptor,
H A DLowerToLLVM.cpp117 cir::LoadOp op, mlir::Value value) { in emitFromMemory()
937 cir::LoadOp op, OpAdaptor adaptor, in matchAndRewrite()
950 mlir::LLVM::LoadOp newLoad = rewriter.create<mlir::LLVM::LoadOp>( in matchAndRewrite()
2557 mlir::Value val = rewriter.create<mlir::LLVM::LoadOp>( in matchAndRewrite()
2648 mlir::Value val = rewriter.create<mlir::LLVM::LoadOp>( in matchAndRewrite()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoXTHead.td749 multiclass LdIdxPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT> {
750 def : Pat<(vt (LoadOp (AddrRegRegScale3 (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), uimm2:$uimm2))),
754 multiclass LdZextIdxPat<PatFrag LoadOp, RVInst Inst, ValueType vt = i64> {
755 def : Pat<(vt (LoadOp (AddrRegZextRegScale3 (i64 GPR:$rs1), (i64 GPR:$rs2), uimm2:$uimm2))),
H A DRISCVInstrInfoXqci.td1290 class QC48LdPat<PatFrag LoadOp, RVInst48 Inst>
1291 : Pat<(i32 (LoadOp (AddLike (i32 GPR:$rs1), simm26_nosimm12:$imm26))),
1300 class QCScaledLdPat<PatFrag LoadOp, RVInst Inst>
1301 : Pat<(i32 (LoadOp (AddrRegRegScale7 (i32 GPRMem:$rs1), (i32 GPRNoX0:$rs2), uimm3:$shamt))),
H A DRISCVInstrInfoXCV.td671 class CVLdrrPat<PatFrag LoadOp, RVInst Inst>
672 : Pat<(XLenVT (LoadOp CVrr:$regreg)),
H A DRISCVInstrInfo.td1949 class LdPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT>
1950 : Pat<(vt (LoadOp (AddrRegImm (XLenVT GPRMem:$rs1), simm12:$imm12))),
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp240 unsigned LoadOp = AMDGPUISD::LOAD_D16_HI; in matchLoadD16FromBuildVector() local
242 LoadOp = LdHi->getExtensionType() == ISD::SEXTLOAD ? in matchLoadD16FromBuildVector()
249 CurDAG->getMemIntrinsicNode(LoadOp, SDLoc(LdHi), VTList, in matchLoadD16FromBuildVector()
268 unsigned LoadOp = AMDGPUISD::LOAD_D16_LO; in matchLoadD16FromBuildVector() local
270 LoadOp = LdLo->getExtensionType() == ISD::SEXTLOAD ? in matchLoadD16FromBuildVector()
283 CurDAG->getMemIntrinsicNode(LoadOp, SDLoc(LdLo), VTList, in matchLoadD16FromBuildVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td1876 multiclass LdPat<PatFrags LoadOp, LAInst Inst, ValueType vt = GRLenVT> {
1877 def : Pat<(vt (LoadOp BaseAddr:$rj)), (Inst BaseAddr:$rj, 0)>;
1878 def : Pat<(vt (LoadOp (AddrConstant GPR:$rj, simm12:$imm12))),
1880 def : Pat<(vt (LoadOp (AddLike BaseAddr:$rj, simm12:$imm12))),
1900 class RegRegLdPat<PatFrag LoadOp, LAInst Inst, ValueType vt>
1901 : Pat<(vt (LoadOp (add NonFIBaseAddr:$rj, GPR:$rk))),
/freebsd/contrib/llvm-project/clang/include/clang/CIR/Dialect/Builder/
H A DCIRBaseBuilder.h217 return create<cir::LoadOp>(loc, addr, /*isDeref=*/false, alignmentAttr); in createDummyValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td4198 multiclass LoadInsertVTPatterns<SDPatternOperator LoadOp, ValueType VT, ValueType ScalarVT,
4205 (ScalarVT (LoadOp (Addr GPR64sp:$Rn, AddrImm:$offset))), (i64 0)),
4209 (ScalarVT (LoadOp (UnscaledAddr GPR64sp:$Rn, simm9:$offset))), (i64 0)),
4213 (ScalarVT (LoadOp (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), (i64 0)),
4217 (ScalarVT (LoadOp (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), (i64 0)),
4222 (ScalarVT (LoadOp (Addr GPR64sp:$Rn, AddrImm:$offset))))),
4225 (ScalarVT (LoadOp (UnscaledAddr GPR64sp:$Rn, simm9:$offset))))),
4228 (ScalarVT (LoadOp (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))))),
4231 (ScalarVT (LoadOp (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))))),
4235 multiclass LoadInsertPatterns<SDPatternOperator LoadOp, ValueType VT, ValueType HVT, ValueType SVT,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td1030 PatFrag LoadOp>
1036 (i32 (LoadOp addrmode6:$Rn)),
1042 PatFrag LoadOp>
1048 (i32 (LoadOp addrmode6oneL32:$Rn)),
1053 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln>,
1056 (i32 (LoadOp addrmode6:$addr)),
1370 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1376 (Ty (ARMvdup (i32 (LoadOp AddrMode:$Rn)))))]>,
1394 class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1400 (Ty (ARMvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
/freebsd/contrib/llvm-project/clang/include/clang/CIR/Dialect/IR/
H A DCIROps.td374 // LoadOp
377 def LoadOp : CIR_Op<"load", [
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp14368 unsigned StoreOp = PPC::STD, LoadOp = PPC::LFD; in EmitInstrWithCustomInserter() local
14377 LoadOp = PPC::LD; in EmitInstrWithCustomInserter()
14408 BuildMI(*BB, MI, dl, TII->get(LoadOp), DestReg) in EmitInstrWithCustomInserter()