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Searched refs:Load2 (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h476 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
494 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
H A DX86InstrInfo.cpp8651 bool X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
8654 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) in areLoadsFromSameBasePtr()
8749 !IsLoadOpcode(Load2->getMachineOpcode())) in areLoadsFromSameBasePtr()
8754 return Load1->getOperand(I) == Load2->getOperand(I); in areLoadsFromSameBasePtr()
8768 auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp)); in areLoadsFromSameBasePtr()
8777 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, in shouldScheduleLoadsNear() argument
8785 unsigned Opc2 = Load2->getMachineOpcode(); in shouldScheduleLoadsNear()
H A DX86ISelLowering.cpp51247 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr2, in combineLoad() local
51252 Load1.getValue(1), Load2.getValue(1)); in combineLoad()
51254 SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2); in combineLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h252 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
263 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
H A DARMBaseInstrInfo.cpp1948 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
1954 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) in areLoadsFromSameBasePtr()
1981 !IsLoadOpcode(Load2->getMachineOpcode())) in areLoadsFromSameBasePtr()
1985 if (Load1->getOperand(0) != Load2->getOperand(0) || in areLoadsFromSameBasePtr()
1986 Load1->getOperand(4) != Load2->getOperand(4)) in areLoadsFromSameBasePtr()
1990 if (Load1->getOperand(3) != Load2->getOperand(3)) in areLoadsFromSameBasePtr()
1995 isa<ConstantSDNode>(Load2->getOperand(1))) { in areLoadsFromSameBasePtr()
1997 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); in areLoadsFromSameBasePtr()
2015 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, in shouldScheduleLoadsNear() argument
2031 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) && in shouldScheduleLoadsNear()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1444 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
1458 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, in shouldScheduleLoadsNear() argument
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp12849 LoadSDNode *Load2 = cast<LoadSDNode>(Op2); in tryToFoldExtendSelectLoad() local
12851 !TLI.isLoadExtLegal(ExtLoadOpcode, VT, Load2->getMemoryVT()) || in tryToFoldExtendSelectLoad()