| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 128 def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_lo)>;
502 def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>;
503 def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>;
504 def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>;
510 def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>;
512 def: Pat<(i1 (trunc I64:$Rs)), (S2_tstbit_i (LoReg $Rs), 0)>;
552 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
555 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
571 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>;
579 (A2_andir (LoReg $Rs), (i32 0x00010001))),
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| H A D | HexagonCopyToCombine.cpp | 750 Register LoReg = LoOperand.getReg(); in emitCombineIR() local
761 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
769 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
776 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
784 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
791 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
849 Register LoReg = LoOperand.getReg(); in emitCombineRR() local
868 .addReg(LoReg, LoRegKillFlag); in emitCombineRR()
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| H A D | HexagonIntrinsics.td | 95 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
97 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
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| H A D | HexagonFrameLowering.cpp | 1119 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo); in insertCFIInstructionsAt() local
1121 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true); in insertCFIInstructionsAt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.h | 52 void splitReg(Register Reg, Register &LoReg, Register &HiReg) const;
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| H A D | AVRRegisterInfo.cpp | 300 void AVRRegisterInfo::splitReg(Register Reg, Register &LoReg, in splitReg() argument
304 LoReg = getSubReg(Reg, AVR::sub_lo); in splitReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcAsmPrinter.cpp | 443 Register HiReg, LoReg; in PrintAsmOperand() local
464 LoReg = RegisterInfo->getSubReg(MOReg, SP::sub_odd); in PrintAsmOperand()
469 Reg = LoReg; in PrintAsmOperand()
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| H A D | SparcISelLowering.cpp | 1316 Register LoReg = VA.getLocReg() + 1; in LowerCall_64() local
1319 LoReg = toCallerWindow(LoReg); in LowerCall_64()
1323 RegsToPass.push_back(std::make_pair(LoReg, Lo64)); in LowerCall_64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 306 Register LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local
323 std::swap(LoReg, HiReg); in expandBuildPairF64()
324 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, in expandBuildPairF64()
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| H A D | MipsSEInstrInfo.cpp | 798 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
827 .addReg(LoReg); in expandBuildPairF64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5700 unsigned LoReg, ROpc, MOpc; in Select() local
5704 LoReg = X86::AL; in Select()
5709 LoReg = X86::AX; in Select()
5714 LoReg = X86::EAX; in Select()
5719 LoReg = X86::RAX; in Select()
5734 SDValue InGlue = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, in Select()
5779 unsigned LoReg, HiReg; in Select() local
5794 LoReg = UseMULX ? X86::EDX : X86::EAX; in Select()
5806 LoReg = UseMULX ? X86::RDX : X86::RAX; in Select()
5820 SDValue InGlue = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 188 Register LoReg; member
2003 assert((TRI->getRegSizeInBits(Addr.Base.LoReg, *MRI) == 32 || in computeBase()
2025 .addReg(Addr.Base.LoReg, 0, Addr.Base.LoSubReg) in computeBase()
2142 Addr.Base.LoReg = BaseLo.getReg(); in processBaseWithConstOffset()
2191 << printReg(MAddr.Base.LoReg, TRI) in promoteConstantOffsetToImm()
2249 if (MAddrNext.Base.LoReg != MAddr.Base.LoReg || in promoteConstantOffsetToImm()
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| H A D | AMDGPUInstructionSelector.cpp | 2476 Register LoReg = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() local
2478 BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), LoReg) in selectG_TRUNC()
2494 .addReg(LoReg, RegState::Implicit); in selectG_TRUNC()
2518 .addReg(LoReg) in selectG_TRUNC()
2833 Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local
2838 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), LoReg) in selectG_FNEG()
2852 .addReg(LoReg) in selectG_FNEG()
2871 Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FABS() local
2880 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), LoReg) in selectG_FABS()
2894 .addReg(LoReg) in selectG_FABS()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 2103 for (unsigned LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; in CMSEPushCalleeSaves() local
2104 --LoReg) { in CMSEPushCalleeSaves()
2105 if (JumpReg == LoReg) in CMSEPushCalleeSaves()
2107 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) in CMSEPushCalleeSaves()
2124 Register LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; in CMSEPushCalleeSaves() local
2125 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) in CMSEPushCalleeSaves()
2130 .addReg(LoReg, RegState::Kill); in CMSEPushCalleeSaves()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 6231 Register LoReg = MI.getOperand(0).getReg(); in emitSplitPairF64Pseudo() local
6235 BuildMI(*BB, MI, DL, TII.get(LoongArch::MOVFR2GR_S_64), LoReg).addReg(SrcReg); in emitSplitPairF64Pseudo()
6254 Register LoReg = MI.getOperand(1).getReg(); in emitBuildPairF64Pseudo() local
6258 .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill())); in emitBuildPairF64Pseudo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 21295 Register LoReg = MI.getOperand(0).getReg(); in emitReadCounterWidePseudo() local
21305 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), LoReg) in emitReadCounterWidePseudo()
21334 Register LoReg = MI.getOperand(0).getReg(); in emitSplitF64Pseudo() local
21348 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg) in emitSplitF64Pseudo()
21371 Register LoReg = MI.getOperand(1).getReg(); in emitBuildPairF64Pseudo() local
21383 .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill())) in emitBuildPairF64Pseudo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 13871 Register LoReg = MI.getOperand(0).getReg(); in EmitInstrWithCustomInserter() local
13875 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268); in EmitInstrWithCustomInserter()
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