Searched refs:LoR (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 787 Register LoR = P.first; in splitShift() local
805 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR) in splitShift()
830 BuildMI(B, MI, DL, TII->get(A2_aslh), LoR) in splitShift()
836 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR)) in splitShift()
857 BuildMI(B, MI, DL, TII->get(S2_insert), LoR) in splitShift()
864 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), (Left ? HiR : LoR)) in splitShift()
867 BuildMI(B, MI, DL, TII->get(A2_tfrsi), (Left ? LoR : HiR)) in splitShift()
879 BuildMI(B, MI, DL, TII->get(A2_asrh), LoR) in splitShift()
882 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR)) in splitShift()
891 BuildMI(B, MI, DL, TII->get(A2_tfrsi), (Left ? LoR : HiR)) in splitShift()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 29736 SDValue LoR = DAG.getBitcast(VT16, getUnpackl(DAG, dl, VT, R, R)); in LowerShift() local
29738 LoR = DAG.getNode(X86OpcI, dl, VT16, LoR, Cst8); in LowerShift()
29740 LoR = DAG.getNode(ISD::MUL, dl, VT16, LoR, LoA); in LowerShift()
29742 LoR = DAG.getNode(X86ISD::VSRLI, dl, VT16, LoR, Cst8); in LowerShift()
29744 return DAG.getNode(X86ISD::PACKUS, dl, VT, LoR, HiR); in LowerShift()
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