| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 707 SDValue Lo1 = Node->getOperand(2); in trySelect() local
711 SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2}; in trySelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 978 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, in SelectADD_SUB_I64() local
996 SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) }; in SelectADD_SUB_I64()
999 SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0), N->getOperand(2) }; in SelectADD_SUB_I64()
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| H A D | AMDGPUInstructionSelector.cpp | 463 MachineOperand Lo1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub0)); in selectG_ADD_SUB() local
473 .add(Lo1) in selectG_ADD_SUB()
484 .add(Lo1) in selectG_ADD_SUB()
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| H A D | SIISelLowering.cpp | 6058 auto [Lo1, Hi1] = DAG.SplitVectorOperand(Op.getNode(), 1); in splitBinaryVectorOp()
6063 DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, Op->getFlags()); in splitBinaryVectorOp()
6086 auto [Lo1, Hi1] = DAG.SplitVectorOperand(Op.getNode(), 1); in splitTernaryVectorOp()
6093 DAG.getNode(Opc, SL, ResVT.first, Lo0, Lo1, Lo2, Op->getFlags()); in splitTernaryVectorOp()
11086 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero); in LowerSELECT() local
11088 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1); in LowerSELECT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 5162 dag Lo1 = (ORI (LIS 0x5555), 0x5555);
5176 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1),
5230 dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32));
5239 dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555);
5248 dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1),
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 4421 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; in SplitVecOp_VSETCC() local
4424 GetSplitVector(N->getOperand(isStrict ? 2 : 1), Lo1, Hi1); in SplitVecOp_VSETCC()
4430 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); in SplitVecOp_VSETCC()
4434 N->getOperand(0), Lo0, Lo1, N->getOperand(3)); in SplitVecOp_VSETCC()
4446 LoRes = DAG.getNode(ISD::VP_SETCC, DL, PartResVT, Lo0, Lo1, in SplitVecOp_VSETCC()
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| H A D | TargetLowering.cpp | 5283 SDValue Lo0, Lo1, Hi0, Hi1; in SimplifySetCC() local
5285 IsConcat(N0.getOperand(1), Lo1, Hi1)) { in SimplifySetCC()
5286 return MergeConcat(DAG.getNode(N0.getOpcode(), dl, OpVT, Lo0, Lo1), in SimplifySetCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9481 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2)); in isExtendedBUILD_VECTOR() local
9483 if (!Lo0 || !Hi0 || !Lo1 || !Hi1) in isExtendedBUILD_VECTOR()
9487 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32) in isExtendedBUILD_VECTOR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 57958 SDValue Accum, Lo0, Lo1, Hi0, Hi1; in combineAdd() local
57962 m_Value(Lo1)), in combineAdd()
57967 concatSubVectors(Lo1, Hi1, DAG, DL)); in combineAdd()
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