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Searched refs:LiveIns (Results 1 – 19 of 19) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp221 for (auto &I : LiveIns) in clearVirtRegs()
487 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) in EmitLiveInCopies()
488 if (LiveIns[i].second) { in EmitLiveInCopies()
489 if (use_nodbg_empty(LiveIns[i].second)) { in EmitLiveInCopies()
495 LiveIns.erase(LiveIns.begin() + i); in EmitLiveInCopies()
500 TII.get(TargetOpcode::COPY), LiveIns[i].second) in EmitLiveInCopies()
501 .addReg(LiveIns[i].first); in EmitLiveInCopies()
504 EntryMBB->addLiveIn(LiveIns[i].first); in EmitLiveInCopies()
508 EntryMBB->addLiveIn(LiveIns[i].first); in EmitLiveInCopies()
H A DMachineBasicBlock.cpp600 LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; }); in removeLiveIn()
601 if (I == LiveIns.end()) in removeLiveIn()
606 LiveIns.erase(I); in removeLiveIn()
612 LiveInVector::iterator LI = LiveIns.begin() + (I - LiveIns.begin()); in removeLiveIn()
613 return LiveIns.erase(LI); in removeLiveIn()
618 LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; }); in isLiveIn()
623 llvm::sort(LiveIns, in sortUniqueLiveIns()
628 LiveInVector::const_iterator I = LiveIns.begin(); in sortUniqueLiveIns()
630 LiveInVector::iterator Out = LiveIns.begin(); in sortUniqueLiveIns()
631 for (; I != LiveIns.end(); ++Out, I = J) { in sortUniqueLiveIns()
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H A DMachineTraceMetrics.cpp808 for (const LiveInReg &LIR : TBI.LiveIns) { in computeCrossBlockCriticalPath()
1029 TBI.LiveIns.push_back(Reg); in addLiveIns()
1047 TBI.LiveIns.clear(); in computeInstrHeights()
1065 for (LiveInReg &LI : TBI.LiveIns) { in computeInstrHeights()
1168 for (LiveInReg &LIR : TBI.LiveIns) { in computeInstrHeights()
1176 TBI.LiveIns.push_back(LiveInReg(RU.RegUnit, RU.Cycle)); in computeInstrHeights()
H A DMachineOutliner.cpp979 LivePhysRegs LiveIns(TRI); in createOutlinedFunction() local
992 LiveIns.addReg(Reg); in createOutlinedFunction()
994 addLiveIns(MBB, LiveIns); in createOutlinedFunction()
H A DRDFGraph.cpp642 LiveIns(PRI) {} in DataFlowGraph()
650 LiveIns(PRI) {} in DataFlowGraph()
916 LiveIns.insert(RegisterRef(P.first)); in build()
919 LiveIns.insert(RegisterRef(I.PhysReg, I.LaneMask)); in build()
923 for (RegisterRef RR : LiveIns.refs()) { in build()
H A DPrologEpilogInserter.cpp1250 BitVector LiveIns(TRI.getNumRegs()); in insertZeroCallUsedRegs() local
1252 LiveIns.set(LI.PhysReg); in insertZeroCallUsedRegs()
1271 if (!LiveIns[Reg.id()]) in insertZeroCallUsedRegs()
H A DRDFLiveness.cpp899 const RegisterAggr &LiveIns = LiveMap[&B]; in resetLiveIns() local
900 for (RegisterRef R : LiveIns.refs()) in resetLiveIns()
H A DMIRPrinter.cpp321 YamlMF.LiveIns.push_back(std::move(LiveIn)); in convertMRI()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSchedStrategy.cpp806 RPTracker.advance(begin(), end(), &LiveIns[RegionIdx]); in getRealRegPressure()
868 LiveIns[CurRegion] = RPTracker.getLiveRegs(); in computeBlockPressure()
939 LiveIns.resize(Regions.size()); in finalizeSchedule()
982 &LiveIns[Stage->getRegionIdx()]; in runSchedStages()
1193 << print(DAG.LiveIns[RegionIdx], DAG.MRI) in initGCNRegion()
1195 << print(llvm::getRegPressure(DAG.MRI, DAG.LiveIns[RegionIdx])) in initGCNRegion()
1862 auto It = DAG.LiveIns[LIRegion].find(Reg); in canIncreaseOccupancyOrReduceSpill()
1863 if (It == DAG.LiveIns[LIRegion].end() || It->second.none()) in canIncreaseOccupancyOrReduceSpill()
1875 if (ReduceRPInRegion(It, Reg, DAG.LiveIns[LIRegion][Reg], in canIncreaseOccupancyOrReduceSpill()
1939 GCNRPTracker::LiveRegSet &RegionLiveIns = DAG.LiveIns[I]; in rematerialize()
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H A DGCNIterativeScheduler.cpp83 const auto LiveIns = getLiveRegsBefore(*Begin, *LIS); in printLivenessInfo() local
84 OS << "LIn RP: " << print(getRegPressure(MRI, LiveIns)); in printLivenessInfo()
H A DGCNSchedStrategy.h260 SmallVector<GCNRPTracker::LiveRegSet, 32> LiveIns; variable
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h152 std::vector<std::pair<MCRegister, Register>> LiveIns; variable
1001 LiveIns.push_back(std::make_pair(Reg, vreg));
1008 livein_iterator livein_begin() const { return LiveIns.begin(); } in livein_begin()
1009 livein_iterator livein_end() const { return LiveIns.end(); } in livein_end()
1010 bool livein_empty() const { return LiveIns.empty(); } in livein_empty()
1013 return LiveIns; in liveins()
H A DMachineBasicBlock.h173 LiveInVector LiveIns;
480 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
483 LiveIns.push_back(RegMaskPair);
520 livein_iterator livein_begin_dbg() const { return LiveIns.begin(); }
526 livein_iterator livein_end() const { return LiveIns.end(); }
527 bool livein_empty() const { return LiveIns.empty(); }
535 const std::vector<RegisterMaskPair> &getLiveIns() const { return LiveIns; }
H A DMachineTraceMetrics.h250 SmallVector<LiveInReg, 4> LiveIns; member
H A DRDFGraph.h700 const RegisterAggr &getLiveIns() const { return LiveIns; } in getLiveIns()
899 RegisterAggr LiveIns; member
H A DMIRYamlMapping.h774 std::vector<MachineFunctionLiveIn> LiveIns;
824 YamlIO.mapOptional("liveins", MF.LiveIns,
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBlockRanges.cpp234 RegisterSet LiveIns; in getLiveIns() local
252 LiveIns.insert(R); in getLiveIns()
255 LiveIns.insert(S); in getLiveIns()
257 return LiveIns; in getLiveIns()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/
H A DInstrRefBasedImpl.cpp3208 SmallVector<DbgValue, 32> LiveIns, LiveOuts; in buildVLocValueMap() local
3209 LiveIns.reserve(NumBlocks); in buildVLocValueMap()
3217 LiveIns.push_back(EmptyDbgValue); in buildVLocValueMap()
3228 LiveInIdx[BlockOrders[I]] = &LiveIns[I]; in buildVLocValueMap()
3240 LiveIns[I] = EmptyDbgValue; in buildVLocValueMap()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp729 for (const auto &LiveIn : YamlMF.LiveIns) { in parseRegisterInfo()