| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3933 bool LegalOps; member
3939 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} in TargetLoweringOpt()
3942 bool LegalOperations() const { return LegalOps; } in LegalOperations()
4405 bool LegalOps, bool OptForSize,
4410 SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize,
4415 getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth);
4431 bool LegalOps, bool OptForSize,
4433 return getCheaperOrNeutralNegatedExpression(Op, DAG, LegalOps, OptForSize,
4439 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
4442 return getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth);
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2341 if (DemandedBits.isOne() && !TLO.LegalOps && !VT.isVector()) in SimplifyDemandedBits()
3495 if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps) { in SimplifyDemandedVectorElts()
7235 bool LegalOps, bool OptForSize, in getNegatedExpression() argument
7284 if (LegalOps && !IsOpLegal) in getNegatedExpression()
7314 if (LegalOps && !IsOpLegal) in getNegatedExpression()
7335 if (LegalOps && !isOperationLegalOrCustom(ISD::FSUB, VT)) in getNegatedExpression()
7342 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
7350 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
7398 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
7406 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 828 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
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| H A D | PPCISelLowering.cpp | 17641 bool LegalOps, bool OptForSize, in getNegatedExpression() argument
17664 getNegatedExpression(N2, DAG, LegalOps, OptForSize, N2Cost, Depth + 1); in getNegatedExpression()
17676 SDValue NegN0 = getNegatedExpression(N0, DAG, LegalOps, OptForSize, in getNegatedExpression()
17680 SDValue NegN1 = getNegatedExpression(N1, DAG, LegalOps, OptForSize, in getNegatedExpression()
17701 return TargetLowering::getNegatedExpression(Op, DAG, LegalOps, OptForSize, in getNegatedExpression()
18131 bool LegalOps = !DCI.isBeforeLegalizeOps(); in combineFMALike() local
18144 if (SDValue NegN0 = getCheaperNegatedExpression(N0, DAG, LegalOps, CodeSize)) in combineFMALike()
18149 if (SDValue NegN1 = getCheaperNegatedExpression(N1, DAG, LegalOps, CodeSize)) in combineFMALike()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 986 if (Op.getOpcode() == ISD::BUILD_VECTOR && TLO.LegalOps && TLO.LegalTys) in shouldSimplifyDemandedVectorElts()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 17709 if (!TLO.LegalOps) in targetShrinkDemandedConstant()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 20200 if (!TLO.LegalOps) in targetShrinkDemandedConstant()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 2266 if (!TLO.LegalOps) in targetShrinkDemandedConstant()
|