| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 4088 bool LegalOps; member
4094 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} in TargetLoweringOpt()
4097 bool LegalOperations() const { return LegalOps; } in LegalOperations()
4580 bool LegalOps, bool OptForSize,
4585 SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize,
4590 getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth);
4606 bool LegalOps, bool OptForSize,
4608 return getCheaperOrNeutralNegatedExpression(Op, DAG, LegalOps, OptForSize,
4614 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
4617 return getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth);
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2409 if (DemandedBits.isOne() && !TLO.LegalOps && !VT.isVector()) in SimplifyDemandedBits()
3649 if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps) { in SimplifyDemandedVectorElts()
7454 bool LegalOps, bool OptForSize, in getNegatedExpression() argument
7503 if (LegalOps && !IsOpLegal) in getNegatedExpression()
7533 if (LegalOps && !IsOpLegal) in getNegatedExpression()
7554 if (LegalOps && !isOperationLegalOrCustom(ISD::FSUB, VT)) in getNegatedExpression()
7561 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
7569 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
7617 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
7625 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 841 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
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| H A D | PPCISelLowering.cpp | 18549 bool LegalOps, bool OptForSize, in getNegatedExpression() argument
18572 getNegatedExpression(N2, DAG, LegalOps, OptForSize, N2Cost, Depth + 1); in getNegatedExpression()
18584 SDValue NegN0 = getNegatedExpression(N0, DAG, LegalOps, OptForSize, in getNegatedExpression()
18588 SDValue NegN1 = getNegatedExpression(N1, DAG, LegalOps, OptForSize, in getNegatedExpression()
18609 return TargetLowering::getNegatedExpression(Op, DAG, LegalOps, OptForSize, in getNegatedExpression()
19133 bool LegalOps = !DCI.isBeforeLegalizeOps(); in combineFMALike() local
19146 if (SDValue NegN0 = getCheaperNegatedExpression(N0, DAG, LegalOps, CodeSize)) in combineFMALike()
19151 if (SDValue NegN1 = getCheaperNegatedExpression(N1, DAG, LegalOps, CodeSize)) in combineFMALike()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1159 if (Op.getOpcode() == ISD::BUILD_VECTOR && TLO.LegalOps && TLO.LegalTys) in shouldSimplifyDemandedVectorElts()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 20134 if (!TLO.LegalOps) in targetShrinkDemandedConstant()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 20831 if (!TLO.LegalOps) in targetShrinkDemandedConstant()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 2503 if (!TLO.LegalOps) in targetShrinkDemandedConstant()
|