| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; }
64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; }
65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; }
66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; }
67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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| H A D | LanaiInstrInfo.cpp | 756 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
760 if (LdSt.getNumOperands() != 4) in getMemOperandWithOffsetWidth()
762 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOperandWithOffsetWidth()
763 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOperandWithOffsetWidth()
766 switch (LdSt.getOpcode()) { in getMemOperandWithOffsetWidth()
787 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
788 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth()
797 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
800 switch (LdSt.getOpcode()) { in getMemOperandsWithOffsetWidth()
814 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
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| H A D | LanaiInstrInfo.h | 73 const MachineInstr &LdSt,
78 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 3134 bool RISCVInstrInfo::isLdStSafeToPair(const MachineInstr &LdSt, in isLdStSafeToPair() argument
3137 if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3) in isLdStSafeToPair()
3140 if (LdSt.getOperand(1).isFI()) in isLdStSafeToPair()
3143 assert(LdSt.getOperand(1).isReg() && "Expected a reg operand."); in isLdStSafeToPair()
3146 if (LdSt.modifiesRegister(LdSt.getOperand(1).getReg(), TRI)) in isLdStSafeToPair()
3149 if (!LdSt.getOperand(2).isImm()) in isLdStSafeToPair()
3156 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
3159 if (!LdSt.mayLoadOrStore()) in getMemOperandsWithOffsetWidth()
3163 switch (LdSt.getOpcode()) { in getMemOperandsWithOffsetWidth()
3193 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
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| H A D | RISCVInstrInfo.h | 185 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
308 static bool isLdStSafeToPair(const MachineInstr &LdSt,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 730 GLoadStore &LdSt = cast<GLoadStore>(I); in select() local
731 LLT PtrTy = MRI.getType(LdSt.getPointerReg()); in select()
741 I.getOpcode(), RBI.getRegBank(LdSt.getReg(0), MRI, TRI)->getID(), in select()
742 LdSt.getMemSizeInBits().getValue()); in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2861 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
2866 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
2872 static bool isLdStSafeToCluster(const MachineInstr &LdSt, in isLdStSafeToCluster() argument
2875 if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3) in isLdStSafeToCluster()
2878 if (LdSt.getOperand(2).isFI()) in isLdStSafeToCluster()
2881 assert(LdSt.getOperand(2).isReg() && "Expected a reg operand."); in isLdStSafeToCluster()
2884 if (LdSt.modifiesRegister(LdSt.getOperand(2).getReg(), TRI)) in isLdStSafeToCluster()
5771 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
5773 if (!LdSt.mayLoadOrStore() || LdSt.getNumExplicitOperands() != 3) in getMemOperandWithOffsetWidth()
5777 if (!LdSt.getOperand(1).isImm() || in getMemOperandWithOffsetWidth()
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| H A D | PPCInstrInfo.h | 668 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
678 const MachineInstr &LdSt,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 363 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
366 if (!LdSt.mayLoadOrStore()) in getMemOperandsWithOffsetWidth()
369 unsigned Opc = LdSt.getOpcode(); in getMemOperandsWithOffsetWidth()
374 if (isDS(LdSt)) { in getMemOperandsWithOffsetWidth()
375 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandsWithOffsetWidth()
376 OffsetOp = getNamedOperand(LdSt, AMDGPU::OpName::offset); in getMemOperandsWithOffsetWidth()
393 Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx)); in getMemOperandsWithOffsetWidth()
399 getNamedOperand(LdSt, AMDGPU::OpName::offset0); in getMemOperandsWithOffsetWidth()
401 getNamedOperand(LdSt, AMDGPU::OpName::offset1); in getMemOperandsWithOffsetWidth()
412 if (LdSt.mayLoad()) in getMemOperandsWithOffsetWidth()
[all …]
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| H A D | SIInstrInfo.h | 252 const MachineInstr &LdSt,
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1211 bool CombinerHelper::isIndexedLoadStoreLegal(GLoadStore &LdSt) const { in isIndexedLoadStoreLegal()
1213 LLT PtrTy = MRI.getType(LdSt.getPointerReg()); in isIndexedLoadStoreLegal()
1214 LLT Ty = MRI.getType(LdSt.getReg(0)); in isIndexedLoadStoreLegal()
1215 LLT MemTy = LdSt.getMMO().getMemoryType(); in isIndexedLoadStoreLegal()
1219 unsigned IndexedOpc = getIndexedOpc(LdSt.getOpcode()); in isIndexedLoadStoreLegal()
1235 bool CombinerHelper::findPostIndexCandidate(GLoadStore &LdSt, Register &Addr, in findPostIndexCandidate() argument
1245 Register Ptr = LdSt.getPointerReg(); in findPostIndexCandidate()
1250 if (!isIndexedLoadStoreLegal(LdSt)) in findPostIndexCandidate()
1256 MachineInstr *StoredValDef = getDefIgnoringCopies(LdSt.getReg(0), MRI); in findPostIndexCandidate()
1277 !TLI.isIndexingLegal(LdSt, PtrAdd->getBaseReg(), Offset, in findPostIndexCandidate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 831 if (auto *LdSt = dyn_cast<GLoadStore>(&MI); in optimizeConsecutiveMemOpAddressing() local
832 LdSt && MRI.getType(LdSt->getOperand(0).getReg()).isScalableVector()) in optimizeConsecutiveMemOpAddressing()
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| H A D | AArch64InstructionSelector.cpp | 3009 GLoadStore &LdSt = cast<GLoadStore>(I); in select() local
3011 LLT PtrTy = MRI.getType(LdSt.getPointerReg()); in select()
3018 uint64_t MemSizeInBytes = LdSt.getMemSize().getValue(); in select()
3019 unsigned MemSizeInBits = LdSt.getMemSizeInBits().getValue(); in select()
3020 AtomicOrdering Order = LdSt.getMMO().getSuccessOrdering(); in select()
3026 assert(!isa<GZExtLoad>(LdSt)); in select()
3030 if (isa<GLoad>(LdSt)) { in select()
3043 Register ValReg = LdSt.getReg(0); in select()
3058 const Register PtrReg = LdSt.getPointerReg(); in select()
3067 const Register ValReg = LdSt.getReg(0); in select()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 2980 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
2983 if (!LdSt.mayLoadOrStore()) in getMemOperandsWithOffsetWidth()
2988 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable, in getMemOperandsWithOffsetWidth()
3996 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
3999 assert(LdSt.mayLoadOrStore() && "Expected a memory operation."); in getMemOperandWithOffsetWidth()
4001 if (LdSt.getNumExplicitOperands() == 3) { in getMemOperandWithOffsetWidth()
4003 if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) || in getMemOperandWithOffsetWidth()
4004 !LdSt.getOperand(2).isImm()) in getMemOperandWithOffsetWidth()
4006 } else if (LdSt.getNumExplicitOperands() == 4) { in getMemOperandWithOffsetWidth()
4008 if (!LdSt.getOperand(1).isReg() || in getMemOperandWithOffsetWidth()
[all …]
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| H A D | AArch64InstrInfo.h | 318 MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const;
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| H A D | AArch64SchedTSV110.td | 135 // MicroOp Count/Types: #(ALU|AB|MDU|FSU1|FSU2|LdSt|ALUAB|F|FLdSt)
138 // 1 micro-ops to be issued down one ALU pipe, six MDU pipes and four LdSt pipes.
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFragmentsSIMD.td | 1013 auto &LdSt = cast<GLoadStore>(MI);
1014 return LdSt.getAlign() >= LdSt.getMemSize().getValue();
1024 auto &LdSt = cast<GLoadStore>(MI);
1025 return LdSt.getAlign() >= LdSt.getMemSize().getValue();
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| H A D | X86InstrInfo.h | 446 const MachineInstr &LdSt,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 209 const MachineInstr &LdSt,
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| H A D | HexagonInstrInfo.cpp | 3077 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
3081 const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width); in getMemOperandsWithOffsetWidth()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 1537 auto *LdSt = dyn_cast<LSBaseSDNode>(MemAccess); in storeLoadIsAligned() local
1546 (LdSt && !LdSt->getOffset().isUndef())) in storeLoadIsAligned()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 1009 bool isIndexedLoadStoreLegal(GLoadStore &LdSt) const;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleR52.td | 551 foreach Num = 1-32 in { // reserve LdSt resource, no dual-issue
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| H A D | ARMISelDAGToDAG.cpp | 1084 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op); in SelectAddrMode6Offset() local
1085 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset()
1090 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits()) in SelectAddrMode6Offset()
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