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Searched refs:Late (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonLoopIdiomRecognition.cpp598 ValueSeq &Late);
599 bool classifyInst(Instruction *UseI, ValueSeq &Early, ValueSeq &Late);
1157 ValueSeq &Cycle, ValueSeq &Early, ValueSeq &Late) { in classifyCycle() argument
1175 ValueSeq &First = !IsE ? Early : Late; in classifyCycle()
1179 ValueSeq &Second = IsE ? Early : Late; in classifyCycle()
1193 ValueSeq &Early, ValueSeq &Late) { in classifyInst() argument
1200 if (Late.count(TV) || Late.count(FV)) in classifyInst()
1203 } else if (Late.count(TV) || Late.count(FV)) { in classifyInst()
1206 Late.insert(UseI); in classifyInst()
1220 else if (Late.count(&*I)) in classifyInst()
[all …]
H A DHexagonInstrFormats.td93 let TSFlags{13} = isPredicateLate; // Late predicate producer insn.
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DSplitKit.h434 bool Late, unsigned RegIdx);
440 bool Late, SlotIndex Def,
H A DSplitKit.cpp530 LiveInterval &DestLI, bool Late, SlotIndex Def, const MCInstrDesc &Desc) { in buildSingleSubRegCopy() argument
539 Def = Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot(); in buildSingleSubRegCopy()
548 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) { in buildCopy() argument
556 return Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot(); in buildCopy()
578 DestLI, Late, Def, Desc); in buildCopy()
600 bool Late = RegIdx != 0; in defFromParent() local
613 Def = Edit->rematerializeAt(MBB, I, Reg, RM, TRI, Late); in defFromParent()
634 Def = Indexes.insertMachineInstrInMaps(*ImplicitDef, Late).getRegSlot(); in defFromParent()
637 Def = buildCopy(Edit->getReg(), Reg, LaneMask, MBB, I, Late, RegIdx); in defFromParent()
H A DLiveRangeEdit.cpp186 bool Late, unsigned SubIdx, in rematerializeAt() argument
199 return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot(); in rematerializeAt()
/freebsd/contrib/unbound/doc/
H A DCREDITS6 Late in 2006, NLnet Labs joined the effort, writing an implementation in C
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h215 bool Late = false, unsigned SubIdx = 0,
H A DSlotIndexes.h531 SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late = false) {
543 if (Late) {
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleR52.td60 // ALU - Write occurs in Late EX2 (independent of whether shift was required)
78 // Branches - LR written in Late EX2
/freebsd/share/misc/
H A Dusb_vendors18437 0210 Blade Pro (Late 2016)
18449 0224 Blade (Late 2016)
18459 0232 Blade Stealth (Late 2017)
18474 024a Blade Stealth (Late 2019)
18475 024b Gaming Laptop [Blade 15 Advanced (Late 2019)]
18476 024c Gaming Laptop [Blade Pro (Late 2019)]
H A Dpci_vendors2483 106b 00e2 MacBookPro8,2 [Core i7, 15", Late 2011]