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Searched refs:Late (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonLoopIdiomRecognition.cpp588 ValueSeq &Late);
589 bool classifyInst(Instruction *UseI, ValueSeq &Early, ValueSeq &Late);
1144 ValueSeq &Cycle, ValueSeq &Early, ValueSeq &Late) { in classifyCycle() argument
1162 ValueSeq &First = !IsE ? Early : Late; in classifyCycle()
1166 ValueSeq &Second = IsE ? Early : Late; in classifyCycle()
1180 ValueSeq &Early, ValueSeq &Late) { in classifyInst() argument
1187 if (Late.count(TV) || Late.count(FV)) in classifyInst()
1190 } else if (Late.count(TV) || Late.count(FV)) { in classifyInst()
1193 Late.insert(UseI); in classifyInst()
1207 else if (Late.count(&*I)) in classifyInst()
[all …]
H A DHexagonInstrFormats.td93 let TSFlags{13} = isPredicateLate; // Late predicate producer insn.
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DSplitKit.h440 bool Late, unsigned RegIdx);
446 bool Late, SlotIndex Def,
H A DSplitKit.cpp529 LiveInterval &DestLI, bool Late, SlotIndex Def, const MCInstrDesc &Desc) { in buildSingleSubRegCopy() argument
538 Def = Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot(); in buildSingleSubRegCopy()
547 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) { in buildCopy() argument
555 return Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot(); in buildCopy()
577 DestLI, Late, Def, Desc); in buildCopy()
629 bool Late = RegIdx != 0; in defFromParent() local
643 SlotIndex Def = Edit->rematerializeAt(MBB, I, Reg, RM, TRI, Late); in defFromParent()
671 Def = Indexes.insertMachineInstrInMaps(*ImplicitDef, Late).getRegSlot(); in defFromParent()
674 Def = buildCopy(Edit->getReg(), Reg, LaneMask, MBB, I, Late, RegIdx); in defFromParent()
H A DLiveRangeEdit.cpp182 bool Late, unsigned SubIdx, in rematerializeAt() argument
195 return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot(); in rematerializeAt()
/freebsd/contrib/unbound/doc/
H A DCREDITS6 Late in 2006, NLnet Labs joined the effort, writing an implementation in C
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h213 bool Late = false, unsigned SubIdx = 0,
H A DSlotIndexes.h532 SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late = false) {
544 if (Late) {
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleR52.td60 // ALU - Write occurs in Late EX2 (independent of whether shift was required)
78 // Branches - LR written in Late EX2
/freebsd/share/misc/
H A Dusb_vendors18495 0210 Blade Pro (Late 2016)
18507 0224 Blade (Late 2016)
18517 0232 Blade Stealth (Late 2017)
18532 024a Blade Stealth (Late 2019)
18533 024b Gaming Laptop [Blade 15 Advanced (Late 2019)]
18534 024c Gaming Laptop [Blade Pro (Late 2019)]
H A Dpci_vendors2524 106b 00e2 MacBookPro8,2 [Core i7, 15", Late 2011]