| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCTargetDesc.cpp | 175 unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) { in HexagonConvertUnits() argument
187 return (*Lanes = 4, CVI_XLANE); in HexagonConvertUnits()
190 return (*Lanes = 2, CVI_XLANE | CVI_MPY0); in HexagonConvertUnits()
192 return (*Lanes = 2, CVI_MPY0); in HexagonConvertUnits()
194 return (*Lanes = 2, CVI_XLANE); in HexagonConvertUnits()
199 return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1); in HexagonConvertUnits()
202 return (*Lanes = 1, CVI_XLANE | CVI_SHIFT); in HexagonConvertUnits()
205 return (*Lanes = 1, CVI_MPY0 | CVI_MPY1); in HexagonConvertUnits()
207 return (*Lanes = 1, CVI_ZW); in HexagonConvertUnits()
209 return (*Lanes = 1, CVI_XLANE); in HexagonConvertUnits()
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| H A D | HexagonShuffler.cpp | 116 unsigned Lanes; in HexagonCVIResource()
117 const unsigned Units = HexagonConvertUnits(ItinUnits, &Lanes); in HexagonCVIResource() local
119 if (Units == 0 && Lanes == 0) { in HexagonCVIResource()
130 setLanes(Lanes); in HexagonCVIResource()
138 unsigned Lanes;
142 static unsigned makeAllBits(unsigned startBit, unsigned Lanes)
144 for (unsigned i = 1; i < Lanes; ++i) in makeAllBits()
157 unsigned allBits = makeAllBits(b, hvxInsts[startIdx].Lanes); in checkHVXPipes()
335 inst.Lanes = I.CVI.getLanes(); in ValidResourceUsage()
139 unsigned Lanes; global() member
143 makeAllBits(unsigned startBit,unsigned Lanes) makeAllBits() argument
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| H A D | HexagonShuffler.h | 76 unsigned Lanes;
82 void setLanes(unsigned l) { Lanes = l; }
92 unsigned getLanes() const { return Lanes; } in isValid()
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| H A D | HexagonMCTargetDesc.h | 102 unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes);
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| /freebsd/contrib/llvm-project/clang/utils/TableGen/ |
| H A D | MveEmitter.cpp | 291 unsigned Lanes; member in __anon819a2c470111::VectorType
294 VectorType(const ScalarType *Element, unsigned Lanes) in VectorType() argument
295 : CRegularNamedType(TypeKind::Vector), Element(Element), Lanes(Lanes) {} in VectorType()
296 unsigned sizeInBits() const override { return Lanes * Element->sizeInBits(); } in sizeInBits()
297 unsigned lanes() const { return Lanes; } in lanes()
301 return Element->cNameBase() + "x" + utostr(Lanes); in cNameBase()
305 utostr(Lanes) + ")"; in llvmName()
343 unsigned Lanes; member in __anon819a2c470111::PredicateType
346 PredicateType(unsigned Lanes) in PredicateType() argument
347 : CRegularNamedType(TypeKind::Predicate), Lanes(Lanes) {} in PredicateType()
[all …]
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| H A D | ClangBuiltinsEmitter.cpp | 135 unsigned long long Lanes; in ParseType() local
136 if (llvm::consumeUnsignedInteger(T, 10, Lanes)) in ParseType()
138 Type += "E" + std::to_string(Lanes); in ParseType()
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| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | fsl-ls1028a-kontron-sl28-var1.dts | 20 model = "Kontron SMARC-sAL28 (4 Lanes)";
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 458 if (!Spill.Lanes.empty()) in allocateVGPRSpillToAGPR()
463 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
506 Spill.Lanes[I] = *NextSpillReg++; in allocateVGPRSpillToAGPR()
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| H A D | SIMachineFunctionInfo.h | 491 SmallVector<MCPhysReg, 32> Lanes;
714 : I->second.Lanes[Lane];
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| H A D | SIISelLowering.cpp | 9204 SmallVector<SDValue, 3> Lanes; in LowerINTRINSIC_W_CHAIN() local
9205 DAG.ExtractVectorElements(Op, Lanes, 0, 3); in LowerINTRINSIC_W_CHAIN()
9206 if (Lanes[0].getValueSizeInBits() == 32) { in LowerINTRINSIC_W_CHAIN()
9208 Ops.push_back(DAG.getBitcast(MVT::i32, Lanes[I])); in LowerINTRINSIC_W_CHAIN()
9214 { Lanes[0], Lanes[1] }))); in LowerINTRINSIC_W_CHAIN()
9215 Ops.push_back(Lanes[2]); in LowerINTRINSIC_W_CHAIN()
9221 { Elt0, Lanes[0] }))); in LowerINTRINSIC_W_CHAIN()
9225 { Lanes[1], Lanes[2] }))); in LowerINTRINSIC_W_CHAIN()
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | nvidia,tegra124-xusb-padctl.txt | 62 Note that not all of these properties are valid for all lanes. Lanes can be
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 834 int Lanes = 1; in getCastInstrCost() local
836 Lanes = SrcTy.getVectorNumElements(); in getCastInstrCost()
839 return Lanes; in getCastInstrCost()
841 return Lanes * CallCost; in getCastInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2059 const size_t Lanes = Op.getNumOperands(); in LowerBUILD_VECTOR() local
2145 for (size_t I = 0; I < Lanes; ++I) { in LowerBUILD_VECTOR()
2257 uint64_t LaneBits = 128 / Lanes; in LowerBUILD_VECTOR()
2289 for (size_t I = 0; I < Lanes; ++I) { in LowerBUILD_VECTOR()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterCoalescer.cpp | 2754 LaneBitmask Lanes = SubRangeJoin ? LaneBitmask::getLane(0) in analyzeValue() local
2756 V.ValidLanes = V.WriteLanes = Lanes; in analyzeValue()
3111 LaneBitmask Lanes) const { in usesLanes()
3120 if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any()) in usesLanes()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ConstantFolding.cpp | 3307 unsigned Lanes = FVTy->getNumElements(); in ConstantFoldFixedVectorCall() local
3311 for (unsigned i = 0; i < Lanes; i++) { in ConstantFoldFixedVectorCall()
3325 unsigned Lanes = FVTy->getNumElements(); in ConstantFoldFixedVectorCall() local
3330 for (unsigned i = 0; i < Lanes; i++) { in ConstantFoldFixedVectorCall()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAArch64.td | 255 // Vector Add Across Lanes
260 // Vector Long Add Across Lanes
358 // Vector Max Across Lanes
374 // Vector Min Across Lanes
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 2274 for (unsigned Lane = 0, Lanes = getNumLanes(); Lane != Lanes; ++Lane) in getVL() local
2301 // fashion. That is, Lanes 2, then Lane 0, and finally Lane 3. in reorder()
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