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Searched refs:LaneIndex (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.cpp351 MachineFunction &MF, int FI, unsigned LaneIndex) { in allocateVirtualVGPRForSGPRSpills() argument
354 if (!LaneIndex) { in allocateVirtualVGPRForSGPRSpills()
361 SGPRSpillsToVirtualVGPRLanes[FI].emplace_back(LaneVGPR, LaneIndex); in allocateVirtualVGPRForSGPRSpills()
366 MachineFunction &MF, int FI, unsigned LaneIndex, bool IsPrologEpilog) { in allocatePhysicalVGPRForSGPRSpills() argument
371 if (!LaneIndex) { in allocatePhysicalVGPRForSGPRSpills()
395 SGPRSpillsToPhysicalVGPRLanes[FI].emplace_back(LaneVGPR, LaneIndex); in allocatePhysicalVGPRForSGPRSpills()
428 unsigned LaneIndex = (NumSpillLanes % WaveSize); in allocateSGPRSpillToVGPRLane() local
431 ? allocatePhysicalVGPRForSGPRSpills(MF, FI, LaneIndex, in allocateSGPRSpillToVGPRLane()
433 : allocateVirtualVGPRForSGPRSpills(MF, FI, LaneIndex); in allocateSGPRSpillToVGPRLane()
H A DSIMachineFunctionInfo.h552 unsigned LaneIndex);
554 unsigned LaneIndex,
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp872 unsigned LaneIndex; member
2170 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; in isVecListOneDByteIndexed()
2175 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; in isVecListOneDHWordIndexed()
2180 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; in isVecListOneDWordIndexed()
2185 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; in isVecListTwoDByteIndexed()
2190 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; in isVecListTwoDHWordIndexed()
2195 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; in isVecListTwoQWordIndexed()
2200 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; in isVecListTwoQHWordIndexed()
2205 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; in isVecListTwoDWordIndexed()
2210 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; in isVecListThreeDByteIndexed()
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