| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 696 auto LaneIdx = getSplatIndex(MI); in matchDupLane() local
697 if (!LaneIdx) in matchDupLane()
701 if (*LaneIdx >= SrcTy.getNumElements()) in matchDupLane()
741 MatchInfo.second = *LaneIdx; in matchDupLane()
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| H A D | AArch64InstructionSelector.cpp | 166 Register EltReg, unsigned LaneIdx,
322 Register VecReg, unsigned LaneIdx,
2752 unsigned LaneIdx = Offset / 64; in select() local
2754 DstReg, DstRB, LLT::scalar(64), SrcReg, LaneIdx, MIB); in select()
3885 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt() argument
3916 if (LaneIdx == 0) { in emitExtractVectorElt()
3935 MIRBuilder.buildInstr(CopyOpc, {*DstReg}, {InsertReg}).addImm(LaneIdx); in emitExtractVectorElt()
3969 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectExtractElt() local
3974 LaneIdx, MIB); in selectExtractElt()
4104 unsigned LaneIdx = 1; in selectUnmergeValues() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 587 int LaneIdx = (Idx / NumEltsPerLane) * NumEltsPerLane; in getHorizDemandedEltsForFirstOperand() local
590 DemandedLHS.setBit(LaneIdx + 2 * LocalIdx); in getHorizDemandedEltsForFirstOperand()
593 DemandedRHS.setBit(LaneIdx + 2 * LocalIdx); in getHorizDemandedEltsForFirstOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 3316 unsigned LaneIdx = Lane * VWidthPerLane; in simplifyDemandedVectorEltsIntrinsic() local
3318 unsigned Idx = LaneIdx + Elt + InnerVWidthPerLane * OpNum; in simplifyDemandedVectorEltsIntrinsic()
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| H A D | X86ISelLowering.cpp | 21783 unsigned LaneIdx = LExtIndex / NumEltsPerLane; in lowerAddSubToHorizontalOp() local
21784 X = extract128BitVector(X, LaneIdx * NumEltsPerLane, DAG, DL); in lowerAddSubToHorizontalOp()
44788 unsigned LaneIdx = LaneOffset / Vec.getScalarValueSizeInBits(); in combineExtractWithShuffle() local
44790 Vec = extract128BitVector(Vec, LaneIdx, DAG, dl); in combineExtractWithShuffle()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 7986 int64_t LaneIdx; in parseSwizzleBroadcast() local
7998 if (parseSwizzleOperand(LaneIdx, in parseSwizzleBroadcast()
8002 Imm = encodeBitmaskPerm(BITMASK_MAX - GroupSize + 1, LaneIdx, 0); in parseSwizzleBroadcast()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrSIMD.td | 66 def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 8176 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32); in LowerBUILD_VECTOR() local
8177 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
15384 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32); in PerformARMBUILD_VECTORCombine() local
15385 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx); in PerformARMBUILD_VECTORCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 14213 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
14217 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); in LowerBUILD_VECTOR()
14371 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
14372 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
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