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Searched refs:LWR (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp230 case Mips::LWR: in isBasePlusOffsetMemoryAccess()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp223 case MipsISD::LWR: return "MipsISD::LWR"; in getTargetNodeName()
2737 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, in lowerLOAD() local
2749 return LWR; in lowerLOAD()
2762 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); in lowerLOAD()
2764 SDValue Ops[] = { SRL, LWR.getValue(1) }; in lowerLOAD()
4812 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) in emitLDR_W()
4881 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) in emitLDR_D()
4892 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) in emitLDR_D()
H A DMipsISelLowering.h251 LWR, enumerator
H A DMipsInstrInfo.cpp658 case Mips::LWR: in HasLoadDelaySlot()
H A DMipsInstructionSelector.cpp482 if (!buildUnalignedLoad(I, Mips::LWR, I.getOperand(0).getReg(), in select()
H A DMipsScheduleP5600.td140 def : InstRW<[P5600WriteLoadShifted], (instrs LWL, LWR, LWLE, LWRE)>;
H A DMipsScheduleGeneric.td569 def : InstRW<[GenericWriteLoad], (instrs LWL, LWR)>;
H A DMipsInstrInfo.td141 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
2129 def LWR : MMRel, LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4590 unsigned XWR = IsLoadInst ? Mips::LWR : Mips::SWR; in expandUxw()