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Searched refs:LWL (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp229 case Mips::LWL: in isBasePlusOffsetMemoryAccess()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.h250 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, enumerator
H A DMipsISelLowering.cpp222 case MipsISD::LWL: return "MipsISD::LWL"; in getTargetNodeName()
2735 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, in lowerLOAD() local
2737 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, in lowerLOAD()
4817 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) in emitLDR_W()
4886 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) in emitLDR_D()
4897 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) in emitLDR_D()
H A DMipsInstrInfo.cpp659 case Mips::LWL: in HasLoadDelaySlot()
H A DMipsInstructionSelector.cpp479 if (!buildUnalignedLoad(I, Mips::LWL, Tmp, BaseAddr, SignedOffset + 3, in select()
H A DMipsScheduleP5600.td140 def : InstRW<[P5600WriteLoadShifted], (instrs LWL, LWR, LWLE, LWRE)>;
H A DMipsScheduleGeneric.td569 def : InstRW<[GenericWriteLoad], (instrs LWL, LWR)>;
H A DMipsInstrInfo.td139 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
2127 def LWL : MMRel, LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4589 unsigned XWL = IsLoadInst ? Mips::LWL : Mips::SWL; in expandUxw()