| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrShiftRotate.td | 15 /// SHL [~] ASR [~] LSR [~] SWAP [ ]
94 defm LSR : MxSROp<"lsr", srl, MxRODI_R, MxROOP_LS>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 35 LSR, enumerator
56 case AArch64_AM::LSR: return "lsr"; in getShiftExtendName()
77 case 1: return AArch64_AM::LSR; in getShiftType()
105 case AArch64_AM::LSR: STEnc = 1; break; in getShifterImm()
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
| H A D | ARMUtils.h | 126 static inline uint32_t LSR(const uint32_t value, const uint32_t amount, in LSR() function
|
| /freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Orc/ |
| H A D | OrcV2CBindings.cpp | 277 LLVMOrcLookupStateRef LSR = ::wrap(OrcV2CAPIHelper::extractLookupState(LS)); in tryToGenerate() local
297 auto Err = unwrap(TryToGenerate(::wrap(this), Ctx, &LSR, CLookupKind, in tryToGenerate()
302 OrcV2CAPIHelper::resetLookupState(LS, ::unwrap(LSR)); in tryToGenerate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedA510.td | 683 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",
684 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",
685 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",
686 "^(ASR|LSL|LSR)_ZPZI_[BHSD]",
687 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",
688 "^(ASR|LSL|LSR)_ZPZZ_[BHSD]",
689 "^(ASR|LSL|LSR)_ZZI_[BHSD]",
|
| H A D | AArch64SchedA320.td | 705 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",
706 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",
707 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",
708 "^(ASR|LSL|LSR)_ZPZI_[BHSD]",
709 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",
710 "^(ASR|LSL|LSR)_ZPZZ_[BHSD]",
711 "^(ASR|LSL|LSR)_ZZI_[BHSD]",
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| H A D | AArch64SchedNeoverseN2.td | 689 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
1666 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",
1667 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",
1668 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",
1669 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",
1670 "^(ASR|LSL|LSR)_ZZI_[BHSD]",
1671 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",
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| H A D | AArch64SchedNeoverseN3.td | 594 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
1636 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",
1637 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",
1638 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",
1639 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",
1640 "^(ASR|LSL|LSR)_ZZI_[BHSD]",
1641 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",
|
| H A D | AArch64SchedPredicates.td | 55 def CheckShiftLSR : CheckImmOperand_s<3, "AArch64_AM::LSR">;
|
| H A D | AArch64SchedNeoverseV1.td | 609 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
616 // Arithmetic, flagset, LSR/ASR/ROR shift or LSL shift > 4
1503 (instregex "^(ASR|LSL|LSR)_WIDE_Z(Pm|Z)Z_[BHS]",
1504 "^(ASR|LSL|LSR)_ZPm[IZ]_[BHSD]",
1505 "^(ASR|LSL|LSR)_ZZI_[BHSD]",
1506 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",
|
| H A D | AArch64SchedNeoverseV2.td | 1130 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
2152 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",
2153 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",
2154 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",
2155 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",
2156 "^(ASR|LSL|LSR)_ZZI_[BHSD]",
2157 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",
|
| H A D | AArch64ISelDAGToDAG.cpp | 662 return AArch64_AM::LSR; in getShiftTypeForNode()
2962 } else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) { in getUsefulBitsFromOrWithShiftedReg()
3497 EncodedShiftImm = AArch64_AM::getShifterImm(AArch64_AM::LSR, SrlImm); in isWorthFoldingIntoOrrWithShift()
3597 AArch64_AM::getShifterImm(AArch64_AM::LSR, SrlImm), DL, VT)}; in tryOrrWithShift()
3760 SDNode *LSR = CurDAG->getMachineNode( in tryBitfieldInsertOpFromOr() local
3769 SDValue Ops[] = {Dst, SDValue(LSR, 0), in tryBitfieldInsertOpFromOr()
|
| H A D | AArch64AsmPrinter.cpp | 808 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56))); in emitHwasanMemaccessSymbols()
881 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56))); in emitHwasanMemaccessSymbols()
|
| H A D | AArch64SchedAmpere1.td | 994 (instregex "(ASR|LSL|LSR|ROR)V(W|X)r")>;
|
| H A D | AArch64SchedAmpere1B.td | 976 (instregex "(ASR|LSL|LSR|ROR)V(W|X)r")>;
|
| H A D | AArch64SchedNeoverseN1.td | 310 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 693 LSR, enumerator
|
| /freebsd/sys/crypto/openssl/arm/ |
| H A D | bsaes-armv7.S | 567 .LSR: label
921 vldmia r6, {q12} @ .LSR
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2711 LatticeCell LSR; in evaluateHexCondMove() local
2712 if (!evaluate(R, LR, LSR)) in evaluateHexCondMove()
2714 RC.meet(LSR); in evaluateHexCondMove()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleM7.td | 338 def : InstRW<[WriteALUsi], (instregex "(t|t2)(LSL|LSR|ASR|ROR)r", "tROR")>;
|
| H A D | ARMInstrThumb.td | 1180 // LSR immediate
1191 // LSR register
|
| H A D | ARMScheduleR52.td | 330 (instregex "ASRr", "RORS?r", "LSR", "LSL")>;
|
| H A D | ARMScheduleM85.td | 439 (instregex "(t|t2)(LSL|LSR|ASR|ROR|SBFX|UBFX)")>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1520 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isShifter()
1622 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isArithmeticShifter()
1633 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isLogicalShifter()
3656 .Case("lsr", AArch64_AM::LSR) in tryParseOptionalShiftExtend()
3679 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.td | 302 defm LSR : ArcBinaryEXT5Inst<0b000001, "lsr">;
|