| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 86 DAG_FUNCTION(lrint, 1, 1, experimental_constrained_lrint, LRINT)
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| H A D | VPIntrinsics.def | 449 VP_PROPERTY_FUNCTIONAL_SDOPC(LRINT)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1042 LRINT, enumerator
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| H A D | BasicTTIImpl.h | 2349 ISD = ISD::LRINT; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 869 ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND}, in initActions()
931 setOperationAction({ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND}, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 432 case ISD::LRINT: return "lrint"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 115 case ISD::LRINT: in ScalarizeVectorResult()
763 case ISD::LRINT: in ScalarizeVectorOperand()
1244 case ISD::LRINT: in SplitVectorResult()
3481 case ISD::LRINT: in SplitVectorOperand()
4891 case ISD::LRINT: in WidenVectorResult()
6839 case ISD::LRINT: in WidenVectorOperand()
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| H A D | LegalizeFloatTypes.cpp | 1160 case ISD::LRINT: Res = SoftenFloatOp_LRINT(N); break; in SoftenFloatOperand()
2301 case ISD::LRINT: Res = ExpandFloatOp_LRINT(N); break; in ExpandFloatOperand()
2627 case ISD::LRINT: in PromoteFloatOperand()
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| H A D | LegalizeDAG.cpp | 1039 case ISD::LRINT: in LegalizeOp()
4468 case ISD::LRINT: in ExpandNode()
4920 case ISD::LRINT: in ConvertNodeToLibcall()
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| H A D | LegalizeVectorOps.cpp | 495 case ISD::LRINT: in LegalizeOp()
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| H A D | LegalizeIntegerTypes.cpp | 352 case ISD::LRINT: in PromoteIntegerResult()
2989 case ISD::LRINT: in ExpandIntegerResult()
4209 } else if (N->getOpcode() == ISD::LRINT || in ExpandIntRes_XROUND_XRINT()
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| H A D | SelectionDAGBuilder.cpp | 6872 case Intrinsic::lrint: Opcode = ISD::LRINT; break; in visitIntrinsicCall()
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| H A D | SelectionDAG.cpp | 5762 case ISD::LRINT: in isKnownNeverNaN()
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| H A D | DAGCombiner.cpp | 1996 case ISD::LRINT: in visit()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 454 ISD::FMAXIMUMNUM, ISD::LRINT, ISD::LLRINT, in RISCVTargetLowering()
513 for (auto Op : {ISD::LROUND, ISD::LLROUND, ISD::LRINT, ISD::LLRINT, in RISCVTargetLowering()
1071 setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom); in RISCVTargetLowering()
1153 setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom); in RISCVTargetLowering()
1456 setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom); in RISCVTargetLowering()
1482 setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom); in RISCVTargetLowering()
1516 ISD::FROUNDEVEN, ISD::FRINT, ISD::LRINT, in RISCVTargetLowering()
3232 case ISD::LRINT: in matchRoundingOp()
7087 case ISD::LRINT: in getRISCVVLOp()
7727 case ISD::LRINT: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 301 setOperationAction(ISD::LRINT, MVT::f32, Custom); in X86TargetLowering()
302 setOperationAction(ISD::LRINT, MVT::f64, Custom); in X86TargetLowering()
307 setOperationAction(ISD::LRINT, MVT::i64, Custom); in X86TargetLowering()
722 setOperationAction(ISD::LRINT, MVT::f16, Expand); in X86TargetLowering()
865 setOperationAction(ISD::LRINT, MVT::f80, Custom); in X86TargetLowering()
1144 setOperationAction(ISD::LRINT, MVT::v4f32, Custom); in X86TargetLowering()
1145 setOperationAction(ISD::LRINT, MVT::v2i32, Custom); in X86TargetLowering()
1479 setOperationAction(ISD::LRINT, MVT::v8f32, Custom); in X86TargetLowering()
1480 setOperationAction(ISD::LRINT, MVT::v4f64, Custom); in X86TargetLowering()
1789 setOperationAction(ISD::LRINT, VT, Legal); in X86TargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 580 def lrint : SDNode<"ISD::LRINT" , SDTFPToIntOp>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 836 for (auto Op : {ISD::LROUND, ISD::LLROUND, ISD::LRINT, ISD::LLRINT, in AArch64TargetLowering()
906 ISD::LLROUND, ISD::LRINT, ISD::LLRINT, in AArch64TargetLowering()
1416 for (auto Op : {ISD::LRINT, ISD::LLRINT}) { in AArch64TargetLowering()
1698 setOperationAction(ISD::LRINT, VT, Custom); in AArch64TargetLowering()
2305 setOperationAction(ISD::LRINT, VT, Default); in addTypeForFixedLengthSVE()
7512 case ISD::LRINT: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 412 setOperationAction({ISD::LRINT, ISD::LLRINT}, {MVT::f16, MVT::f32, MVT::f64}, in AMDGPUTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 573 setOperationAction(ISD::LRINT, MVT::f64, Legal); in PPCTargetLowering()
574 setOperationAction(ISD::LRINT, MVT::f32, Legal); in PPCTargetLowering()
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