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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeUtils.h26 static void DistributeRange(LiveRangeT &LR, LiveRangeT *SplitLRs[], in DistributeRange() argument
29 typename LiveRangeT::iterator J = LR.begin(), E = LR.end(); in DistributeRange()
40 LR.segments.erase(J, E); in DistributeRange()
43 unsigned j = 0, e = LR.getNumValNums(); in DistributeRange()
47 VNInfo *VNI = LR.getValNumInfo(i); in DistributeRange()
53 LR.valnos[j++] = VNI; in DistributeRange()
56 LR.valnos.resize(j); in DistributeRange()
H A DLiveRangeCalc.cpp81 Updater.setDest(&I.LR); in updateFromLiveIns()
87 void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg, in extend() argument
97 auto EP = LR.extendInBlock(Undefs, Indexes->getMBBStartIdx(UseMBB), Use); in extend()
105 if (findReachingDefs(LR, *UseMBB, Use, PhysReg, Undefs)) in extend()
122 bool LiveRangeCalc::isDefOnEntry(LiveRange &LR, ArrayRef<SlotIndex> Undefs, in isDefOnEntry() argument
156 // If LR has a segment S that starts at the next block, i.e. [End, ...), in isDefOnEntry()
159 LiveRange::iterator UB = upper_bound(LR, End.getPrevSlot()); in isDefOnEntry()
160 if (UB != LR.begin()) { in isDefOnEntry()
167 if (LR.isUndefIn(Undefs, Seg.end, End)) in isDefOnEntry()
175 if (UndefOnEntry[N] || LR in isDefOnEntry()
191 findReachingDefs(LiveRange & LR,MachineBasicBlock & UseMBB,SlotIndex Use,unsigned PhysReg,ArrayRef<SlotIndex> Undefs) findReachingDefs() argument
398 LiveRange &LR = I.LR; updateSSA() local
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H A DLiveInterval.cpp67 LiveRange *LR; member in __anon418b83490111::CalcLiveRangeUtilBase
70 CalcLiveRangeUtilBase(LiveRange *LR) : LR(LR) {} in CalcLiveRangeUtilBase() argument
94 VNInfo *VNI = ForVNI ? ForVNI : LR->getNextValue(Def, *VNInfoAllocator); in createDeadDef()
115 VNInfo *VNI = ForVNI ? ForVNI : LR->getNextValue(Def, *VNInfoAllocator); in createDeadDef()
142 return std::make_pair(nullptr, LR->isUndefIn(Undefs, StartIdx, BeforeUse)); in extendInBlock()
145 return std::make_pair(nullptr, LR->isUndefIn(Undefs, StartIdx, BeforeUse)); in extendInBlock()
147 if (LR->isUndefIn(Undefs, I->end, BeforeUse)) in extendInBlock()
288 CalcLiveRangeUtilVector(LiveRange *LR) argument
314 CalcLiveRangeUtilSet(LiveRange * LR) CalcLiveRangeUtilSet() argument
1304 Classify(const LiveRange & LR) Classify() argument
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H A DLiveIntervals.cpp137 for (LiveRange *LR : RegUnitRanges) in clear()
138 delete LR; in clear()
174 if (LiveRange *LR = RegUnitRanges[Unit]) in print() local
175 OS << printRegUnit(Unit, TRI) << ' ' << *LR << '\n'; in print()
296 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) { in computeRegUnitRange() argument
310 LICalc->createDeadDefs(LR, Reg); in computeRegUnitRange()
327 LICalc->extendToUses(LR, Reg); in computeRegUnitRange()
334 LR.flushSegmentSet(); in computeRegUnitRange()
358 LiveRange *LR = RegUnitRanges[Unit]; in computeLiveInRegUnits() local
359 if (!LR) { in computeLiveInRegUnits()
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H A DLiveRegMatrix.cpp178 LiveIntervalUnion::Query &LiveRegMatrix::query(const LiveRange &LR, in query() argument
181 Q.init(UserTag, LR, Matrix[RegUnit]); in query()
201 [&](MCRegister Unit, const LiveRange &LR) { in checkInterference() argument
202 return query(LR, Unit).checkInterference(); in checkInterference()
215 LiveRange LR; in checkInterference() local
216 LR.addSegment(Seg); in checkInterference()
233 Q.reset(UserTag, LR, Matrix[Unit]); in checkInterference()
H A DLiveIntervalCalc.cpp33 LiveRange &LR, const MachineOperand &MO) { in createDeadDef()
38 // Create the def in LR. This may find an existing def. in createDeadDef()
39 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
123 void LiveIntervalCalc::createDeadDefs(LiveRange &LR, Register Reg) {
130 // LR.createDeadDef() will deduplicate. in createDeadDefs()
132 createDeadDef(*Indexes, *Alloc, LR, MO); in createDeadDefs()
135 void LiveIntervalCalc::extendToUses(LiveRange &LR, Register Reg,
193 extend(LR, UseIdx, Reg, Undefs); in extendToUses()
34 createDeadDef(SlotIndexes & Indexes,VNInfo::Allocator & Alloc,LiveRange & LR,const MachineOperand & MO) createDeadDef() argument
124 createDeadDefs(LiveRange & LR,Register Reg) createDeadDefs() argument
136 extendToUses(LiveRange & LR,Register Reg,LaneBitmask Mask,LiveInterval * LI) extendToUses() argument
H A DMachineVerifier.cpp265 void report_context(const LiveRange &LR, Register VRegUnit,
271 void report_context_liverange(const LiveRange &LR) const;
280 SlotIndex UseIdx, const LiveRange &LR,
284 SlotIndex DefIdx, const LiveRange &LR,
597 void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit, in report_context() argument
599 report_context_liverange(LR); in report_context()
613 void MachineVerifier::report_context_liverange(const LiveRange &LR) const { in report_context_liverange()
614 errs() << "- liverange: " << LR << '\n'; in report_context_liverange()
2714 const LiveRange &LR, in checkLivenessAtUse() argument
2718 LiveQueryResult LRQ = LR.Query(UseIdx); in checkLivenessAtUse()
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H A DPHIElimination.cpp486 for (auto LR : ToUpdate) { in LowerPHINode() local
487 auto DestSegment = LR->find(MBBStartIndex); in LowerPHINode()
488 assert(DestSegment != LR->end() && in LowerPHINode()
491 if (LR->endIndex().isDead()) { in LowerPHINode()
495 VNInfo *OrigDestVNI = LR->getVNInfoAt(DestSegment->start); in LowerPHINode()
497 LR->removeSegment(DestSegment->start, DestSegment->start.getDeadSlot()); in LowerPHINode()
498 LR->createDeadDef(NewStart, LIS->getVNInfoAllocator()); in LowerPHINode()
499 LR->removeValNo(OrigDestVNI); in LowerPHINode()
507 VNInfo *VNI = LR->getVNInfoAt(DestSegment->start); in LowerPHINode()
509 LR->addSegment( in LowerPHINode()
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H A DRegAllocFast.cpp360 void allocVirtReg(MachineInstr &MI, LiveReg &LR, Register Hint,
683 for (const LiveReg &LR : LiveVirtRegs) { in reloadAtBegin() local
684 MCPhysReg PhysReg = LR.PhysReg; in reloadAtBegin()
699 reload(MBB.begin(), LR.VirtReg, PhysReg); in reloadAtBegin()
701 reload(InsertBefore, LR.VirtReg, PhysReg); in reloadAtBegin()
839 void RegAllocFastImpl::assignVirtToPhysReg(MachineInstr &AtMI, LiveReg &LR, in assignVirtToPhysReg() argument
841 Register VirtReg = LR.VirtReg; in assignVirtToPhysReg()
844 assert(LR.PhysReg == 0 && "Already assigned a physreg"); in assignVirtToPhysReg()
846 LR.PhysReg = PhysReg; in assignVirtToPhysReg()
891 void RegAllocFastImpl::allocVirtReg(MachineInstr &MI, LiveReg &LR, in allocVirtReg() argument
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H A DLiveIntervalUnion.cpp140 if (LR->empty() || LiveUnion->empty()) { in collectInterferingVRegs()
145 // In most cases, the union will start before LR. in collectInterferingVRegs()
146 LRI = LR->begin(); in collectInterferingVRegs()
151 LiveRange::const_iterator LREnd = LR->end(); in collectInterferingVRegs()
154 assert(LRI != LREnd && "Reached end of LR"); in collectInterferingVRegs()
178 LRI = LR->advanceTo(LRI, LiveUnionI.start()); in collectInterferingVRegs()
H A DRegisterCoalescer.cpp1611 if (LiveRange *LR = LIS->getCachedRegUnit(Unit)) in reMaterializeTrivialDef() local
1612 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator()); in reMaterializeTrivialDef()
1624 if (LiveRange *LR = LIS->getCachedRegUnit(Unit)) in reMaterializeTrivialDef() local
1625 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator()); in reMaterializeTrivialDef()
2324 LiveRange &LR = LIS->getRegUnit(Unit); in joinReservedPhysReg() local
2325 LR.createDeadDef(DestRegIdx, LIS->getVNInfoAllocator()); in joinReservedPhysReg()
2407 LiveRange &LR; member in __anonf9586a8a0311::JoinVals
2589 JoinVals(LiveRange &LR, Register Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals() argument
2593 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask), in JoinVals()
2596 TRI(TRI), Assignments(LR.getNumValNums(), -1), in JoinVals()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRangeCalc.h103 LiveRange &LR; member
117 LiveInBlock(LiveRange &LR, MachineDomTreeNode *node, SlotIndex kill) in LiveInBlock()
118 : LR(LR), DomNode(node), Kill(kill) {} in LiveInBlock()
129 bool isDefOnEntry(LiveRange &LR, ArrayRef<SlotIndex> Undefs,
149 bool findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, SlotIndex Use,
207 void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg,
243 void addLiveInBlock(LiveRange &LR, MachineDomTreeNode *DomNode,
245 LiveIn.push_back(LiveInBlock(LR, DomNode, Kill));
H A DLiveIntervals.h201 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices,
204 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices) { in extendToIndices() argument
205 extendToIndices(LR, Indices, /*Undefs=*/{}); in extendToIndices()
215 void pruneValue(LiveRange &LR, SlotIndex Kill,
256 bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const { in isLiveInToMBB() argument
257 return LR.liveAt(getMBBStartIdx(mbb)); in isLiveInToMBB()
260 bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const { in isLiveOutOfMBB() argument
261 return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot()); in isLiveOutOfMBB()
405 LiveRange *LR = RegUnitRanges[Unit]; in getRegUnit() local
406 if (!LR) { in getRegUnit()
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H A DLiveIntervalCalc.h39 void extendToUses(LiveRange &LR, Register Reg, LaneBitmask LaneMask,
48 void createDeadDefs(LiveRange &LR, Register Reg);
54 void extendToUses(LiveRange &LR, MCRegister PhysReg) { in extendToUses() argument
55 extendToUses(LR, PhysReg, LaneBitmask::getAll()); in extendToUses()
H A DLiveIntervalUnion.h114 const LiveRange *LR = nullptr; variable
132 Query(const LiveRange &LR, const LiveIntervalUnion &LIU) in Query() argument
133 : LiveUnion(&LIU), LR(&LR) {} in Query()
140 LR = &NewLR; in reset()
150 if (UserTag == NewUserTag && LR == &NewLR && LiveUnion == &NewLiveUnion && in init()
/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/GSYM/
H A DFunctionInfo.cpp184 LookupResult LR; in lookup() local
185 LR.LookupAddr = Addr; in lookup()
187 LR.FuncRange = {FuncAddr, FuncAddr + Data.getU32(&Offset)}; in lookup()
198 if (LR.FuncRange.size() > 0 && !LR.FuncRange.contains(Addr)) in lookup()
206 LR.FuncName = GR.getString(NameOffset); in lookup()
250 SrcLoc.Name = LR.FuncName; in lookup()
252 LR.Locations.push_back(SrcLoc); in lookup()
253 return LR; in lookup()
263 SrcLoc.Name = LR in lookup()
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H A DLookupResult.cpp60 raw_ostream &llvm::gsym::operator<<(raw_ostream &OS, const LookupResult &LR) { in operator <<() argument
61 OS << HEX64(LR.LookupAddr) << ": "; in operator <<()
62 auto NumLocations = LR.Locations.size(); in operator <<()
69 OS << LR.Locations[I]; in operator <<()
H A DDwarfTransformer.cpp665 auto LR = Gsym->lookup(Addr); in verify() local
666 if (!LR) in verify()
667 return LR.takeError(); in verify()
684 NumDwarfInlineInfos != LR->Locations.size()) { in verify()
689 << LR->Locations.size() << "\n"; in verify()
696 Log << " " << LR->Locations.size() << " GSYM frames:\n"; in verify()
697 for (size_t Idx = 0, count = LR->Locations.size(); Idx < count; in verify()
699 const auto &gii = LR->Locations[Idx]; in verify()
709 for (size_t Idx = 0, count = LR->Locations.size(); Idx < count; in verify()
711 const auto &gii = LR->Locations[Idx]; in verify()
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/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Orc/
H A DEPCGenericDylibManager.cpp49 static size_t size(const ExecutorProcessControl::LookupRequest &LR) { in size() argument
50 return MemberSerialization::size(ExecutorAddr(LR.Handle), LR.Symbols); in size()
54 const ExecutorProcessControl::LookupRequest &LR) { in serialize() argument
55 return MemberSerialization::serialize(OB, ExecutorAddr(LR.Handle), in serialize()
56 LR.Symbols); in serialize()
/freebsd/sys/arm/arm/
H A Ddb_trace.c81 state->registers[LR]); in db_stack_trace_cmd()
82 db_printsym(state->registers[LR], DB_STGY_PROC); in db_stack_trace_cmd()
89 ~((1 << SP) | (1 << FP) | (1 << LR) | (1 << PC)); in db_stack_trace_cmd()
146 state.registers[LR] = ctx->pcb_regs.sf_lr; in db_trace_thread()
166 state.registers[LR] = (uint32_t)__builtin_return_address(0); in db_trace_self()
/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/
H A DPointerSubChecker.cpp115 const MemRegion *LR = LV.getAsRegion(); in checkPreStmt() local
117 if (!LR || !RR) in checkPreStmt()
121 if (LR == RR) in checkPreStmt()
125 if (isa<SymbolicRegion>(LR) || isa<SymbolicRegion>(RR)) in checkPreStmt()
128 const auto *ElemLR = dyn_cast<ElementRegion>(LR); in checkPreStmt()
133 if (!checkArrayBounds(C, B->getRHS(), ElemRR, LR)) in checkPreStmt()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td270 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
275 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
288 def CSR_ATPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
294 LR, R11)>;
308 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R11,
317 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
323 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
331 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
335 : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12),
344 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
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H A DARMRegisterInfo.td96 def LR : ARMReg<14, "lr", [], ["r14"]>, DwarfRegNum<[14]>;
228 SP, LR, PC)> {
229 // Allocate LR as the first CSR since it is always saved anyway.
234 let AltOrders = [(add LR, GPR), (trunc GPR, 8),
235 (add (trunc GPR, 8), R12, LR, (shl GPR, 8))];
245 def GPRnoip : RegisterClass<"ARM", [i32], 32, (sub GPR, R12, LR)> {
246 // Allocate LR as the first CSR since it is always saved anyway.
263 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8),
264 (add (trunc GPRnopc, 8), R12, LR, (shl GPRnopc, 8))];
275 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LowerHomogeneousPrologEpilog.cpp333 auto LRIdx = std::distance(Regs.begin(), llvm::find(Regs, AArch64::LR)); in getOrCreateFrameHelper()
338 assert(Regs[Size - 2] != AArch64::LR); in getOrCreateFrameHelper()
346 if (Regs[I - 1] == AArch64::LR) in getOrCreateFrameHelper()
360 .addReg(AArch64::LR); in getOrCreateFrameHelper()
370 .addUse(AArch64::LR) in getOrCreateFrameHelper()
381 .addReg(Type == FrameHelperType::Epilog ? AArch64::X16 : AArch64::LR); in getOrCreateFrameHelper()
406 if (!llvm::is_contained(Regs, AArch64::LR)) in shouldUseFrameHelper()
565 if (MO.getReg() == AArch64::LR) in lowerProlog()
589 emitStore(MF, MBB, MBBI, *TII, AArch64::LR, AArch64::FP, -LRIdx - 2, true); in lowerProlog()
601 emitStore(MF, MBB, MBBI, *TII, AArch64::LR, AArch64::FP, -LRIdx - 2, true); in lowerProlog()
H A DAArch64CallingConvention.td519 // FP, LR, and X18
547 // requires the frame-record (LR, FP) to be at the top the callee-save area,
550 // FIXME: LR is only callee-saved in the sense that *we* preserve it and are
552 // is currently safe since BL has LR as an implicit-def and what happens after a
557 // end up saving LR as part of a call frame). Watch this space...
559 X25, X26, X27, X28, LR, FP,
567 // Win64 has unwinding codes for an (FP,LR) pair, save_fplr and save_fplr_x.
568 // We put FP before LR, so that frame lowering logic generates (FP,LR) pairs,
569 // and not (LR,FP) pairs.
571 X25, X26, X27, X28, FP, LR,
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