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Searched refs:LR (Results 1 – 25 of 200) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeUtils.h26 static void DistributeRange(LiveRangeT &LR, LiveRangeT *SplitLRs[], in DistributeRange() argument
29 typename LiveRangeT::iterator J = LR.begin(), E = LR.end(); in DistributeRange()
40 LR.segments.erase(J, E); in DistributeRange()
43 unsigned j = 0, e = LR.getNumValNums(); in DistributeRange()
47 VNInfo *VNI = LR.getValNumInfo(i); in DistributeRange()
53 LR.valnos[j++] = VNI; in DistributeRange()
56 LR.valnos.resize(j); in DistributeRange()
H A DLiveInterval.cpp67 LiveRange *LR; member in __anon418b83490111::CalcLiveRangeUtilBase
70 CalcLiveRangeUtilBase(LiveRange *LR) : LR(LR) {} in CalcLiveRangeUtilBase() argument
94 VNInfo *VNI = ForVNI ? ForVNI : LR->getNextValue(Def, *VNInfoAllocator); in createDeadDef()
115 VNInfo *VNI = ForVNI ? ForVNI : LR->getNextValue(Def, *VNInfoAllocator); in createDeadDef()
142 return std::make_pair(nullptr, LR->isUndefIn(Undefs, StartIdx, BeforeUse)); in extendInBlock()
145 return std::make_pair(nullptr, LR->isUndefIn(Undefs, StartIdx, BeforeUse)); in extendInBlock()
147 if (LR->isUndefIn(Undefs, I->end, BeforeUse)) in extendInBlock()
288 CalcLiveRangeUtilVector(LiveRange *LR) : CalcLiveRangeUtilVectorBase(LR) {} in CalcLiveRangeUtilVector() argument
293 LiveRange::Segments &segmentsColl() { return LR->segments; } in segmentsColl()
295 void insertAtEnd(const Segment &S) { LR->segments.push_back(S); } in insertAtEnd()
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H A DLiveRangeCalc.cpp80 Updater.setDest(&I.LR); in updateFromLiveIns()
86 void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, Register PhysReg, in extend() argument
96 auto EP = LR.extendInBlock(Undefs, Indexes->getMBBStartIdx(UseMBB), Use); in extend()
104 if (findReachingDefs(LR, *UseMBB, Use, PhysReg, Undefs)) in extend()
121 bool LiveRangeCalc::isDefOnEntry(LiveRange &LR, ArrayRef<SlotIndex> Undefs, in isDefOnEntry() argument
158 LiveRange::iterator UB = upper_bound(LR, End.getPrevSlot()); in isDefOnEntry()
159 if (UB != LR.begin()) { in isDefOnEntry()
166 if (LR.isUndefIn(Undefs, Seg.end, End)) in isDefOnEntry()
174 if (UndefOnEntry[N] || LR.isUndefIn(Undefs, Begin, End)) { in isDefOnEntry()
190 bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, in findReachingDefs() argument
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H A DLiveIntervals.cpp153 for (LiveRange *LR : RegUnitRanges) in clear()
154 delete LR; in clear()
190 if (LiveRange *LR = RegUnitRanges[Unit]) in print() local
191 OS << printRegUnit(Unit, TRI) << ' ' << *LR << '\n'; in print()
312 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) { in computeRegUnitRange() argument
326 LICalc->createDeadDefs(LR, Reg); in computeRegUnitRange()
343 LICalc->extendToUses(LR, Reg); in computeRegUnitRange()
350 LR.flushSegmentSet(); in computeRegUnitRange()
374 LiveRange *LR = RegUnitRanges[Unit]; in computeLiveInRegUnits() local
375 if (!LR) { in computeLiveInRegUnits()
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H A DLiveRegMatrix.cpp186 LiveIntervalUnion::Query &LiveRegMatrix::query(const LiveRange &LR, in query() argument
189 Q.init(UserTag, LR, Matrix[RegUnit]); in query()
209 [&](MCRegUnit Unit, const LiveRange &LR) { in checkInterference() argument
210 return query(LR, Unit).checkInterference(); in checkInterference()
223 LiveRange LR; in checkInterference() local
224 LR.addSegment(Seg); in checkInterference()
241 Q.reset(UserTag, LR, Matrix[Unit]); in checkInterference()
254 LiveRange LR; in checkInterferenceLanes() local
255 LR.addSegment(Seg); in checkInterferenceLanes()
275 Q.reset(UserTag, LR, Matrix[Unit]); in checkInterferenceLanes()
H A DLiveIntervalCalc.cpp32 LiveRange &LR, const MachineOperand &MO) { in createDeadDef() argument
38 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
122 void LiveIntervalCalc::createDeadDefs(LiveRange &LR, Register Reg) { in createDeadDefs() argument
131 createDeadDef(*Indexes, *Alloc, LR, MO); in createDeadDefs()
134 void LiveIntervalCalc::extendToUses(LiveRange &LR, Register Reg, in extendToUses() argument
192 extend(LR, UseIdx, Reg, Undefs); in extendToUses()
H A DRegAllocFast.cpp359 void allocVirtReg(MachineInstr &MI, LiveReg &LR, Register Hint,
370 MCPhysReg getErrorAssignment(const LiveReg &LR, MachineInstr &MI,
700 for (const LiveReg &LR : LiveVirtRegs) { in reloadAtBegin() local
701 MCPhysReg PhysReg = LR.PhysReg; in reloadAtBegin()
702 if (PhysReg == 0 || LR.Error) in reloadAtBegin()
716 reload(MBB.begin(), LR.VirtReg, PhysReg); in reloadAtBegin()
718 reload(InsertBefore, LR.VirtReg, PhysReg); in reloadAtBegin()
858 void RegAllocFastImpl::assignVirtToPhysReg(MachineInstr &AtMI, LiveReg &LR, in assignVirtToPhysReg() argument
860 Register VirtReg = LR.VirtReg; in assignVirtToPhysReg()
863 assert(LR.PhysReg == 0 && "Already assigned a physreg"); in assignVirtToPhysReg()
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H A DMachineVerifier.cpp316 void report_context(const LiveRange &LR, VirtRegOrUnit VRegOrUnit,
322 void report_context_liverange(const LiveRange &LR) const;
331 SlotIndex UseIdx, const LiveRange &LR,
335 SlotIndex DefIdx, const LiveRange &LR,
638 void MachineVerifier::report_context(const LiveRange &LR, in report_context() argument
641 report_context_liverange(LR); in report_context()
655 void MachineVerifier::report_context_liverange(const LiveRange &LR) const { in report_context_liverange()
656 OS << "- liverange: " << LR << '\n'; in report_context_liverange()
2843 const LiveRange &LR, in checkLivenessAtUse() argument
2848 if (!LR.verify()) { in checkLivenessAtUse()
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H A DPHIElimination.cpp494 for (auto LR : ToUpdate) { in LowerPHINode() local
495 auto DestSegment = LR->find(MBBStartIndex); in LowerPHINode()
496 assert(DestSegment != LR->end() && in LowerPHINode()
499 if (LR->endIndex().isDead()) { in LowerPHINode()
503 VNInfo *OrigDestVNI = LR->getVNInfoAt(DestSegment->start); in LowerPHINode()
505 LR->removeSegment(DestSegment->start, DestSegment->start.getDeadSlot()); in LowerPHINode()
506 LR->createDeadDef(NewStart, LIS->getVNInfoAllocator()); in LowerPHINode()
507 LR->removeValNo(OrigDestVNI); in LowerPHINode()
515 VNInfo *VNI = LR->getVNInfoAt(DestSegment->start); in LowerPHINode()
517 LR->addSegment( in LowerPHINode()
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H A DRegisterCoalescer.cpp1370 LiveRange &LR = LIS->getRegUnit(Unit); in reMaterializeTrivialDef() local
1371 if (LR.liveAt(CopyIdx)) in reMaterializeTrivialDef()
1668 if (LiveRange *LR = LIS->getCachedRegUnit(Unit)) in reMaterializeTrivialDef() local
1669 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator()); in reMaterializeTrivialDef()
1681 if (LiveRange *LR = LIS->getCachedRegUnit(Unit)) in reMaterializeTrivialDef() local
1682 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator()); in reMaterializeTrivialDef()
2384 LiveRange &LR = LIS->getRegUnit(Unit); in joinReservedPhysReg() local
2385 LR.createDeadDef(DestRegIdx, LIS->getVNInfoAllocator()); in joinReservedPhysReg()
2467 LiveRange &LR; member in __anonf9586a8a0311::JoinVals
2650 JoinVals(LiveRange &LR, Register Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals() argument
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H A DLiveIntervalUnion.cpp140 if (LR->empty() || LiveUnion->empty()) { in collectInterferingVRegs()
146 LRI = LR->begin(); in collectInterferingVRegs()
151 LiveRange::const_iterator LREnd = LR->end(); in collectInterferingVRegs()
178 LRI = LR->advanceTo(LRI, LiveUnionI.start()); in collectInterferingVRegs()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRangeCalc.h104 LiveRange &LR; member
118 LiveInBlock(LiveRange &LR, MachineDomTreeNode *node, SlotIndex kill) in LiveInBlock()
119 : LR(LR), DomNode(node), Kill(kill) {} in LiveInBlock()
130 bool isDefOnEntry(LiveRange &LR, ArrayRef<SlotIndex> Undefs,
150 bool findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, SlotIndex Use,
208 LLVM_ABI void extend(LiveRange &LR, SlotIndex Use, Register PhysReg,
244 void addLiveInBlock(LiveRange &LR, MachineDomTreeNode *DomNode,
246 LiveIn.push_back(LiveInBlock(LR, DomNode, Kill));
H A DLiveIntervals.h211 LLVM_ABI void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices,
214 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices) { in extendToIndices() argument
215 extendToIndices(LR, Indices, /*Undefs=*/{}); in extendToIndices()
225 LLVM_ABI void pruneValue(LiveRange &LR, SlotIndex Kill,
266 bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const { in isLiveInToMBB() argument
267 return LR.liveAt(getMBBStartIdx(mbb)); in isLiveInToMBB()
270 bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const { in isLiveOutOfMBB() argument
271 return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot()); in isLiveOutOfMBB()
416 LiveRange *LR = RegUnitRanges[Unit]; in getRegUnit() local
417 if (!LR) { in getRegUnit()
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H A DLiveIntervalCalc.h40 LLVM_ABI void extendToUses(LiveRange &LR, Register Reg, LaneBitmask LaneMask,
49 LLVM_ABI void createDeadDefs(LiveRange &LR, Register Reg);
55 void extendToUses(LiveRange &LR, MCRegister PhysReg) { in extendToUses() argument
56 extendToUses(LR, PhysReg, LaneBitmask::getAll()); in extendToUses()
H A DLiveIntervalUnion.h114 const LiveRange *LR = nullptr; variable
132 Query(const LiveRange &LR, const LiveIntervalUnion &LIU) in Query() argument
133 : LiveUnion(&LIU), LR(&LR) {} in Query()
140 LR = &NewLR; in reset()
150 if (UserTag == NewUserTag && LR == &NewLR && LiveUnion == &NewLiveUnion && in init()
/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/GSYM/
H A DLookupResult.cpp58 raw_ostream &llvm::gsym::operator<<(raw_ostream &OS, const LookupResult &LR) { in operator <<() argument
59 OS << HEX64(LR.LookupAddr) << ": "; in operator <<()
60 auto NumLocations = LR.Locations.size(); in operator <<()
67 OS << LR.Locations[I]; in operator <<()
72 if (!LR.CallSiteFuncRegex.empty()) { in operator <<()
74 for (size_t i = 0; i < LR.CallSiteFuncRegex.size(); ++i) { in operator <<()
77 OS << LR.CallSiteFuncRegex[i]; in operator <<()
H A DFunctionInfo.cpp242 LookupResult LR; in lookup() local
243 LR.LookupAddr = Addr; in lookup()
245 LR.FuncRange = {FuncAddr, FuncAddr + Data.getU32(&Offset)}; in lookup()
256 if (LR.FuncRange.size() > 0 && !LR.FuncRange.contains(Addr)) in lookup()
264 LR.FuncName = GR.getString(NameOffset); in lookup()
312 LR.CallSiteFuncRegex.push_back(GR.getString(RegexOffset)); in lookup()
332 SrcLoc.Name = LR.FuncName; in lookup()
334 LR.Locations.push_back(SrcLoc); in lookup()
335 return LR; in lookup()
345 SrcLoc.Name = LR.FuncName; in lookup()
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H A DDwarfTransformer.cpp733 auto LR = Gsym->lookup(Addr); in verify() local
734 if (!LR) in verify()
735 return LR.takeError(); in verify()
752 NumDwarfInlineInfos != LR->Locations.size()) { in verify()
757 << LR->Locations.size() << "\n"; in verify()
764 Log << " " << LR->Locations.size() << " GSYM frames:\n"; in verify()
765 for (size_t Idx = 0, count = LR->Locations.size(); Idx < count; in verify()
767 const auto &gii = LR->Locations[Idx]; in verify()
776 for (size_t Idx = 0, count = LR->Locations.size(); Idx < count; in verify()
778 const auto &gii = LR->Locations[Idx]; in verify()
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/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/
H A DPointerSubChecker.cpp49 const MemRegion *LR = LV.getAsRegion(); in checkPreStmt() local
51 if (!LR || !RR) in checkPreStmt()
55 if (LR == RR) in checkPreStmt()
60 if (LR->getSymbolicBase() || RR->getSymbolicBase()) in checkPreStmt()
67 const auto *ElemLR = dyn_cast<ElementRegion>(LR); in checkPreStmt()
74 if (ElemRR && ElemRR->getSuperRegion() == LR) in checkPreStmt()
/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Orc/
H A DEPCGenericDylibManager.cpp49 static size_t size(const DylibManager::LookupRequest &LR) { in size() argument
50 return MemberSerialization::size(ExecutorAddr(LR.Handle), LR.Symbols); in size()
54 const DylibManager::LookupRequest &LR) { in serialize() argument
55 return MemberSerialization::serialize(OB, ExecutorAddr(LR.Handle), in serialize()
56 LR.Symbols); in serialize()
/freebsd/sys/arm/arm/
H A Ddb_trace.c81 state->registers[LR]); in db_stack_trace_cmd()
82 db_printsym(state->registers[LR], DB_STGY_PROC); in db_stack_trace_cmd()
89 ~((1 << SP) | (1 << FP) | (1 << LR) | (1 << PC)); in db_stack_trace_cmd()
146 state.registers[LR] = ctx->pcb_regs.sf_lr; in db_trace_thread()
166 state.registers[LR] = (uint32_t)__builtin_return_address(0); in db_trace_self()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td275 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
284 def CSR_ATPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
290 LR, R11)>;
297 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
320 LR, R11,
322 def CSR_AAPCS_SplitPush_R7 : CalleeSavedRegs<(add LR, R11,
331 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
337 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
345 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
349 : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12),
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H A DThumb1FrameLowering.cpp218 case ARM::LR: in emitPrologue()
279 MBBI->getOperand(0).getReg() == ARM::LR && in emitPrologue()
364 case ARM::LR: in emitPrologue()
577 if (CSI.getReg() == ARM::LR) in needPopSpecialFixUp()
690 GPRsNoLRSP.reset(ARM::LR); in emitPopSpecialFixUp()
730 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
788 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
804 ARM::R7, ARM::LR};
809 ARM::R5, ARM::R6, ARM::R7, ARM::LR};
815 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) { in splitLowAndHighRegs()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td542 // FP, LR, and X18
570 // requires the frame-record (LR, FP) to be at the top the callee-save area,
573 // FIXME: LR is only callee-saved in the sense that *we* preserve it and are
575 // is currently safe since BL has LR as an implicit-def and what happens after a
580 // end up saving LR as part of a call frame). Watch this space...
582 X25, X26, X27, X28, LR, FP,
590 // Win64 has unwinding codes for an (FP,LR) pair, save_fplr and save_fplr_x.
591 // We put FP before LR, so that frame lowering logic generates (FP,LR) pairs,
592 // and not (LR,FP) pairs.
594 X25, X26, X27, X28, FP, LR,
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H A DAArch64LowerHomogeneousPrologEpilog.cpp323 auto LRIdx = std::distance(Regs.begin(), llvm::find(Regs, AArch64::LR)); in getOrCreateFrameHelper()
328 assert(Regs[Size - 2] != AArch64::LR); in getOrCreateFrameHelper()
336 if (Regs[I - 1] == AArch64::LR) in getOrCreateFrameHelper()
350 .addReg(AArch64::LR); in getOrCreateFrameHelper()
360 .addUse(AArch64::LR) in getOrCreateFrameHelper()
371 .addReg(Type == FrameHelperType::Epilog ? AArch64::X16 : AArch64::LR); in getOrCreateFrameHelper()
396 if (!llvm::is_contained(Regs, AArch64::LR)) in shouldUseFrameHelper()
555 if (MO.getReg() == AArch64::LR) in lowerProlog()
579 emitStore(MF, MBB, MBBI, *TII, AArch64::LR, AArch64::FP, -LRIdx - 2, true); in lowerProlog()
591 emitStore(MF, MBB, MBBI, *TII, AArch64::LR, AArch64::FP, -LRIdx - 2, true); in lowerProlog()

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