Searched refs:LN0 (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 7285 auto *LN0 = cast<LoadSDNode>(N0); in visitAND() local
7286 EVT MemVT = LN0->getMemoryVT(); in visitAND()
7293 ((!LegalOperations && LN0->isSimple()) || in visitAND()
7296 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, LN0->getChain(), in visitAND()
7297 LN0->getBasePtr(), MemVT, LN0->getMemOperand()); in visitAND()
13060 LoadSDNode *LN0 = cast<LoadSDNode>(N0); in CombineExtLoad() local
13062 if (!ISD::isNON_EXTLoad(LN0) || !ISD::isUNINDEXEDLoad(LN0) || in CombineExtLoad()
13063 !N0.hasOneUse() || !LN0->isSimple() || in CombineExtLoad()
13096 SDValue BasePtr = LN0->getBasePtr(); in CombineExtLoad()
13101 DAG.getExtLoad(ExtType, SDLoc(LN0), SplitDstVT, LN0->getChain(), in CombineExtLoad()
[all …]
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| H A D | TargetLowering.cpp | 4580 } else if (auto *LN0 = dyn_cast<LoadSDNode>(N0)) { in SimplifySetCC() local
4582 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { in SimplifySetCC()
4583 MinBits = LN0->getMemoryVT().getSizeInBits(); in SimplifySetCC()
4585 } else if (LN0->getExtensionType() == ISD::SEXTLOAD) { in SimplifySetCC()
4587 MinBits = LN0->getMemoryVT().getSizeInBits(); in SimplifySetCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 15202 if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(Op0)) { in PerformVMOVhrCombine() local
15203 if (LN0->hasOneUse() && LN0->isUnindexed() && in PerformVMOVhrCombine()
15204 LN0->getMemoryVT() == MVT::i16) { in PerformVMOVhrCombine()
15206 DCI.DAG.getLoad(N->getValueType(0), SDLoc(N), LN0->getChain(), in PerformVMOVhrCombine()
15207 LN0->getBasePtr(), LN0->getMemOperand()); in PerformVMOVhrCombine()
15235 LoadSDNode *LN0 = cast<LoadSDNode>(N0); in PerformVMOVrhCombine() local
15238 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT, LN0->getChain(), in PerformVMOVrhCombine()
15239 LN0->getBasePtr(), MVT::i16, LN0->getMemOperand()); in PerformVMOVrhCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 18562 LoadSDNode *LN0 = cast<LoadSDNode>(N0); in performIntToFpCombine() local
18563 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(), in performIntToFpCombine()
18564 LN0->getPointerInfo(), LN0->getAlign(), in performIntToFpCombine()
18565 LN0->getMemOperand()->getFlags()); in performIntToFpCombine()
18569 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1)); in performIntToFpCombine()
24987 LoadSDNode *LN0 = cast<LoadSDNode>(N0); in performFPExtendCombine() local
24989 LN0->getChain(), LN0->getBasePtr(), in performFPExtendCombine()
24990 N0.getValueType(), LN0->getMemOperand()); in performFPExtendCombine()
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