Searched refs:LMUL_1 (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/ |
| H A D | RISCVTargetParser.h | 53 LMUL_1 = 0, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/TargetParser/ |
| H A D | RISCVTargetParser.cpp | 177 case RISCVII::VLMUL::LMUL_1: in decodeVLMUL()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/ |
| H A D | RISCVCustomBehaviour.cpp | 114 case RISCVII::LMUL_1: in createInstruments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 259 case RISCVII::VLMUL::LMUL_1: in createTuple()
1632 CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_1, M1, B8) in Select()
1692 CASE_VMSLT_OPCODES(LMUL_1, M1, B8) in Select()
1711 CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_1, M1) in Select()
3666 case RISCVII::LMUL_1: in GetVMSetForLMul()
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| H A D | RISCVInsertVSETVLI.cpp | 533 RISCVII::VLMUL VLMul = RISCVII::LMUL_1;
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| H A D | RISCVInstrInfo.cpp | 288 // In widening reduction instructions with LMUL_1 input vector case, in isConvertibleToVMV_V_V()
290 // always LMUL_1. in isConvertibleToVMV_V_V()
365 return {RISCVII::LMUL_1, RISCV::VRRegClass, RISCV::VMV1R_V, in copyPhysRegVector()
381 return {RISCVII::LMUL_1, RISCV::VRRegClass, RISCV::VMV1R_V, in copyPhysRegVector()
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| H A D | RISCVISelLowering.cpp | 2465 return RISCVII::VLMUL::LMUL_1; in getLMUL()
2482 case RISCVII::VLMUL::LMUL_1: in getRegClassIDForLMUL()
2498 LMUL == RISCVII::VLMUL::LMUL_1) { in getSubregIndexByMVT()
2853 // TODO: Here assume reciprocal throughput is 1 for LMUL_1, it is in getLMULCost()
10386 getLMUL(ContainerSubVecVT) == RISCVII::VLMUL::LMUL_1); in lowerEXTRACT_SUBVECTOR()
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