| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 87 DAG_FUNCTION(llrint, 1, 1, experimental_constrained_llrint, LLRINT)
|
| H A D | VPIntrinsics.def | 455 VP_PROPERTY_FUNCTIONAL_SDOPC(LLRINT)
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1043 LLRINT, enumerator
|
| H A D | BasicTTIImpl.h | 2352 ISD = ISD::LLRINT; in getTypeBasedIntrinsicInstrCost()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 869 ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND}, in initActions()
931 setOperationAction({ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND}, in initActions()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 434 case ISD::LLRINT: return "llrint"; in getOperationName()
|
| H A D | LegalizeVectorTypes.cpp | 116 case ISD::LLRINT: in ScalarizeVectorResult()
764 case ISD::LLRINT: in ScalarizeVectorOperand()
1246 case ISD::LLRINT: in SplitVectorResult()
3482 case ISD::LLRINT: in SplitVectorOperand()
4892 case ISD::LLRINT: in WidenVectorResult()
6840 case ISD::LLRINT: in WidenVectorOperand()
|
| H A D | LegalizeFloatTypes.cpp | 1162 case ISD::LLRINT: Res = SoftenFloatOp_LLRINT(N); break; in SoftenFloatOperand()
2302 case ISD::LLRINT: Res = ExpandFloatOp_LLRINT(N); break; in ExpandFloatOperand()
2628 case ISD::LLRINT: R = PromoteFloatOp_UnaryOp(N, OpNo); break; in PromoteFloatOperand()
|
| H A D | LegalizeDAG.cpp | 1040 case ISD::LLRINT: in LegalizeOp()
4469 case ISD::LLRINT: { in ExpandNode()
4927 case ISD::LLRINT: in ConvertNodeToLibcall()
|
| H A D | LegalizeVectorOps.cpp | 496 case ISD::LLRINT: in LegalizeOp()
|
| H A D | LegalizeIntegerTypes.cpp | 353 case ISD::LLRINT: in PromoteIntegerResult()
2993 case ISD::LLRINT: ExpandIntRes_XROUND_XRINT(N, Lo, Hi); break; in ExpandIntegerResult()
4235 } else if (N->getOpcode() == ISD::LLRINT || in ExpandIntRes_XROUND_XRINT()
|
| H A D | SelectionDAGBuilder.cpp | 6873 case Intrinsic::llrint: Opcode = ISD::LLRINT; break; in visitIntrinsicCall()
|
| H A D | SelectionDAG.cpp | 5763 case ISD::LLRINT: in isKnownNeverNaN()
|
| H A D | DAGCombiner.cpp | 1997 case ISD::LLRINT: return visitXROUND(N); in visit()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 454 ISD::FMAXIMUMNUM, ISD::LRINT, ISD::LLRINT, in RISCVTargetLowering()
513 for (auto Op : {ISD::LROUND, ISD::LLROUND, ISD::LRINT, ISD::LLRINT, in RISCVTargetLowering()
1071 setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom); in RISCVTargetLowering()
1153 setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom); in RISCVTargetLowering()
1456 setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom); in RISCVTargetLowering()
1482 setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom); in RISCVTargetLowering()
1517 ISD::LLRINT, ISD::LROUND, ISD::LLROUND, in RISCVTargetLowering()
3233 case ISD::LLRINT: in matchRoundingOp()
7089 case ISD::LLRINT: in getRISCVVLOp()
7728 case ISD::LLRINT: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 581 def llrint : SDNode<"ISD::LLRINT" , SDTFPToIntOp>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 303 setOperationAction(ISD::LLRINT, MVT::f32, Custom); in X86TargetLowering()
304 setOperationAction(ISD::LLRINT, MVT::f64, Custom); in X86TargetLowering()
308 setOperationAction(ISD::LLRINT, MVT::i64, Custom); in X86TargetLowering()
723 setOperationAction(ISD::LLRINT, MVT::f16, Expand); in X86TargetLowering()
866 setOperationAction(ISD::LLRINT, MVT::f80, Custom); in X86TargetLowering()
1790 setOperationAction(ISD::LLRINT, VT, Legal); in X86TargetLowering()
1835 setOperationAction(ISD::LLRINT, MVT::v8f64, Legal); in X86TargetLowering()
2301 setOperationAction(ISD::LLRINT, MVT::f16, Legal); in X86TargetLowering()
2350 setOperationAction(ISD::LLRINT, MVT::v8f16, Legal); in X86TargetLowering()
2668 ISD::LLRINT, in X86TargetLowering()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 836 for (auto Op : {ISD::LROUND, ISD::LLROUND, ISD::LRINT, ISD::LLRINT, in AArch64TargetLowering()
906 ISD::LLROUND, ISD::LRINT, ISD::LLRINT, in AArch64TargetLowering()
1416 for (auto Op : {ISD::LRINT, ISD::LLRINT}) { in AArch64TargetLowering()
1699 setOperationAction(ISD::LLRINT, VT, Custom); in AArch64TargetLowering()
2306 setOperationAction(ISD::LLRINT, VT, Default); in addTypeForFixedLengthSVE()
7513 case ISD::LLRINT: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 412 setOperationAction({ISD::LRINT, ISD::LLRINT}, {MVT::f16, MVT::f32, MVT::f64}, in AMDGPUTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 575 setOperationAction(ISD::LLRINT, MVT::f64, Legal); in PPCTargetLowering()
576 setOperationAction(ISD::LLRINT, MVT::f32, Legal); in PPCTargetLowering()
|