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Searched refs:LIS (Results 1 – 25 of 124) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMaskingPreRA.cpp34 LiveIntervals *LIS; member in __anon314e3b690111::SIOptimizeExecMaskingPreRA
47 SIOptimizeExecMaskingPreRA(LiveIntervals *LIS) : LIS(LIS) {} in SIOptimizeExecMaskingPreRA() argument
99 LiveIntervals *LIS, Register Reg, in isDefBetween() argument
101 SlotIndex AndIdx = LIS->getInstructionIndex(And).getRegSlot(); in isDefBetween()
102 SlotIndex SelIdx = LIS->getInstructionIndex(Sel).getRegSlot(); in isDefBetween()
105 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx); in isDefBetween()
108 if (isDefBetween(LIS->getRegUnit(Unit), AndIdx, SelIdx)) in isDefBetween()
140 TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, *I, *MRI, LIS); in optimizeVcndVcmpPair()
156 auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, *MRI, LIS); in optimizeVcndVcmpPair()
173 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, *MRI, LIS); in optimizeVcndVcmpPair()
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H A DAMDGPURewriteAGPRCopyMFMA.cpp51 LiveIntervals &LIS; member in __anone22991190111::AMDGPURewriteAGPRCopyMFMAImpl
55 LiveRegMatrix &LRM, LiveIntervals &LIS) in AMDGPURewriteAGPRCopyMFMAImpl() argument
58 LIS(LIS) {} in AMDGPURewriteAGPRCopyMFMAImpl()
119 LiveInterval &LI = LIS.getInterval(VReg); in run()
123 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def); in run()
134 LiveInterval &CopySrcLI = LIS.getInterval(CopySrcReg); in run()
136 MachineInstr *CopySrcMI = LIS.getInstructionFromIndex(LRQ.valueIn()->def); in run()
216 LIS.RemoveMachineInstrFromMaps(*DefMI); in run()
224 LIS.removeInterval(CopySrcReg); in run()
225 LIS.removeInterval(VReg); in run()
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H A DSILowerControlFlow.cpp76 LiveIntervals *LIS = nullptr; member in __anon0c226a110111::SILowerControlFlow
140 SILowerControlFlow(LiveIntervals *LIS, LiveVariables *LV, in SILowerControlFlow() argument
142 : LIS(LIS), LV(LV), MDT(MDT) {} in SILowerControlFlow()
286 if (!LIS) { in emitIf()
291 LIS->InsertMachineInstrInMaps(*CopyExec); in emitIf()
295 LIS->ReplaceMachineInstrInMaps(MI, *And); in emitIf()
298 LIS->InsertMachineInstrInMaps(*Xor); in emitIf()
299 LIS->InsertMachineInstrInMaps(*SetExec); in emitIf()
300 LIS->InsertMachineInstrInMaps(*NewBr); in emitIf()
302 LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC); in emitIf()
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H A DSIWholeQuadMode.cpp154 SIWholeQuadMode(MachineFunction &MF, LiveIntervals *LIS, in SIWholeQuadMode() argument
157 TRI(&TII->getRegisterInfo()), MRI(&MF.getRegInfo()), LIS(LIS), MDT(MDT), in SIWholeQuadMode()
166 LiveIntervals *LIS; member in __anonf56fbe7e0111::SIWholeQuadMode
331 LiveQueryResult UseLRQ = LR.Query(LIS->getInstructionIndex(UseMI)); in markDefs()
370 const MachineBasicBlock *MBB = LIS->getMBBFromIndex(Value->def); in markDefs()
378 if (const VNInfo *VN = LR.getVNInfoBefore(LIS->getMBBEndIdx(*PI))) { in markDefs()
388 MachineInstr *MI = LIS->getInstructionFromIndex(Value->def); in markDefs()
414 LiveQueryResult LRQ = LR.Query(LIS->getInstructionIndex(*MI)); in markDefs()
461 LiveRange &LR = LIS->getInterval(Reg); in markOperand()
468 LiveRange &LR = LIS->getRegUnit(Unit); in markOperand()
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H A DGCNPreRAOptimizations.cpp53 LiveIntervals *LIS; member in __anon021209ff0111::GCNPreRAOptimizationsImpl
58 GCNPreRAOptimizationsImpl(LiveIntervals *LS) : LIS(LS) {} in GCNPreRAOptimizationsImpl()
192 LIS->removeInterval(RegToUpdate); in processReg()
193 LIS->createAndComputeVirtRegInterval(RegToUpdate); in processReg()
207 if (SlotIndex::isEarlierInstr(LIS->getInstructionIndex(*Def1), in processReg()
208 LIS->getInstructionIndex(*Def0))) in processReg()
211 LIS->RemoveMachineInstrFromMaps(*Def0); in processReg()
212 LIS->RemoveMachineInstrFromMaps(*Def1); in processReg()
219 LIS->InsertMachineInstrInMaps(*NewI); in processReg()
220 LIS->removeInterval(Reg); in processReg()
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H A DSILowerWWMCopies.cpp36 SILowerWWMCopies(LiveIntervals *LIS, SlotIndexes *SI, VirtRegMap *VRM) in SILowerWWMCopies() argument
37 : LIS(LIS), Indexes(SI), VRM(VRM) {} in SILowerWWMCopies()
44 LiveIntervals *LIS; member in __anon72eb24b60111::SILowerWWMCopies
89 if (!LIS) in isSCCLiveAtMI()
93 LIS->getRegUnit(*MCRegUnitIterator(MCRegister::from(AMDGPU::SCC), TRI)); in isSCCLiveAtMI()
94 SlotIndex Idx = LIS->getInstructionIndex(MI); in isSCCLiveAtMI()
113 auto *LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr; in runOnMachineFunction() local
121 SILowerWWMCopies Impl(LIS, Indexes, VRM); in runOnMachineFunction()
128 auto *LIS = MFAM.getCachedResult<LiveIntervalsAnalysis>(MF); in run() local
132 SILowerWWMCopies Impl(LIS, Indexes, VRM); in run()
H A DSILowerSGPRSpills.cpp45 LiveIntervals *LIS = nullptr; member in __anoneec5f4eb0111::SILowerSGPRSpills
55 SILowerSGPRSpills(LiveIntervals *LIS, SlotIndexes *Indexes, in SILowerSGPRSpills() argument
57 : LIS(LIS), Indexes(Indexes), MDT(MDT) {} in SILowerSGPRSpills()
115 LiveIntervals *LIS) { in insertCSRSaves() argument
147 if (LIS) in insertCSRSaves()
148 LIS->removeAllRegUnitsForPhysReg(Reg); in insertCSRSaves()
155 if (LIS) in insertCSRSaves()
157 LIS->removeAllRegUnitsForPhysReg(CS.getReg()); in insertCSRSaves()
164 SlotIndexes *Indexes, LiveIntervals *LIS) { in insertCSRRestores() argument
187 if (LIS) in insertCSRRestores()
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H A DAMDGPUMarkLastScratchLoad.cpp31 LiveIntervals *LIS = nullptr; member in __anonbeb091f80111::AMDGPUMarkLastScratchLoad
36 AMDGPUMarkLastScratchLoad(LiveStacks *LS, LiveIntervals *LIS, SlotIndexes *SI) in AMDGPUMarkLastScratchLoad() argument
37 : LS(LS), LIS(LIS), SI(SI) {} in AMDGPUMarkLastScratchLoad()
70 auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS(); in runOnMachineFunction() local
73 return AMDGPUMarkLastScratchLoad(&LS, &LIS, &SI).run(MF); in runOnMachineFunction()
80 auto &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF); in run() local
83 AMDGPUMarkLastScratchLoad(&LS, &LIS, &SI).run(MF); in run()
93 SlotIndexes &Slots = *LIS->getSlotIndexes(); in run()
H A DGCNRegPressure.cpp268 const MachineInstr &MI, const LiveIntervals &LIS, in collectVirtualRegUses() argument
293 auto &LI = LIS.getInterval(P.RegUnit); in collectVirtualRegUses()
301 InstrSI = LIS.getInstructionIndex(MI).getBaseIndex(); in collectVirtualRegUses()
309 const LiveIntervals &LIS, const MachineRegisterInfo &MRI, in getLanesWithProperty() argument
314 const LiveInterval &LI = LIS.getInterval(RegUnit); in getLanesWithProperty()
329 const LiveRange *LR = LIS.getCachedRegUnit(RegUnit); in getLanesWithProperty()
343 const LiveIntervals *LIS, in findUseBetween() argument
349 SlotIndex InstSlot = LIS->getInstructionIndex(*MI).getRegSlot(); in findUseBetween()
431 const LiveIntervals &LIS, in getLiveLaneMask() argument
434 return getLiveLaneMask(LIS.getInterval(Reg), SI, MRI, LaneMaskFilter); in getLiveLaneMask()
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H A DGCNRegPressure.h268 const LiveIntervals &LIS;
274 GCNRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {} in GCNRPTracker()
300 GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS,
314 GCNRPTracker::reset(MRI, llvm::getLiveRegs(SI, LIS, MRI)); in reset()
320 LIS.getSlotIndexes()->getMBBEndIdx(&MBB)); in reset()
325 reset(MI.getMF()->getRegInfo(), LIS.getInstructionIndex(MI).getDeadSlot()); in reset()
426 const LiveIntervals &LIS,
434 GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS,
444 getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) { in getLiveRegMap() argument
447 auto &SII = *LIS.getSlotIndexes(); in getLiveRegMap()
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H A DSIFormMemoryClauses.cpp49 LiveIntervals *LIS; member in __anon72ebc0cc0111::SIFormMemoryClausesImpl
56 SIFormMemoryClausesImpl(LiveIntervals *LS) : LIS(LS) {} in SIFormMemoryClausesImpl()
271 SlotIndexes *Ind = LIS->getSlotIndexes(); in run()
280 GCNDownwardRPTracker RPT(*LIS); in run()
337 SlotIndex ClauseLiveInIdx = LIS->getInstructionIndex(MI); in run()
339 LIS->getInstructionIndex(*LastClauseInst).getNextIndex(); in run()
353 const LiveInterval &LI = LIS->getInterval(R.first); in run()
406 LIS->removeInterval(Reg); in run()
407 LIS->createAndComputeVirtRegInterval(Reg); in run()
414 LIS->removeInterval(Reg); in run()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp270 const LiveIntervals *LIS) { in getVRegDef() argument
276 if (LIS != nullptr) { in getVRegDef()
277 SlotIndex InstIndex = LIS->getInstructionIndex(*Insert); in getVRegDef()
278 if (const VNInfo *ValNo = LIS->getInterval(Reg).getVNInfoBefore(InstIndex)) in getVRegDef()
279 return LIS->getInstructionFromIndex(ValNo->def); in getVRegDef()
290 MachineInstr *Def, LiveIntervals *LIS) { in hasSingleUse() argument
307 if (LIS == nullptr) in hasSingleUse()
311 const LiveInterval &LI = LIS->getInterval(Reg); in hasSingleUse()
313 LI.getVNInfoAt(LIS->getInstructionIndex(*Def).getRegSlot()); in hasSingleUse()
316 const auto &Result = LI.Query(LIS->getInstructionIndex(*I.getParent())); in hasSingleUse()
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H A DWebAssemblyMemIntrinsicResults.cpp88 LiveIntervals &LIS) { in replaceDominatedUses() argument
91 LiveInterval *FromLI = &LIS.getInterval(FromReg); in replaceDominatedUses()
92 LiveInterval *ToLI = &LIS.getInterval(ToReg); in replaceDominatedUses()
94 SlotIndex FromIdx = LIS.getInstructionIndex(MI).getRegSlot(); in replaceDominatedUses()
108 SlotIndex WhereIdx = LIS.getInstructionIndex(*Where); in replaceDominatedUses()
133 LIS.extendToIndices(*ToLI, Indices); in replaceDominatedUses()
136 LIS.shrinkToUses(FromLI); in replaceDominatedUses()
150 MachineDominatorTree &MDT, LiveIntervals &LIS, in optimizeCall() argument
173 return replaceDominatedUses(MBB, MI, FromReg, ToReg, MRI, MDT, LIS); in optimizeCall()
188 auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS(); in runOnMachineFunction() local
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H A DWebAssemblyOptimizeLiveIntervals.cpp79 auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS(); in runOnMachineFunction() local
95 LIS.splitSeparateComponents(LIS.getInterval(Reg), SplitLIs); in runOnMachineFunction()
115 LiveInterval &LI = LIS.getInterval(MI.getOperand(0).getReg()); in runOnMachineFunction()
116 LIS.removeVRegDefAt(LI, LIS.getInstructionIndex(MI).getRegSlot()); in runOnMachineFunction()
117 LIS.RemoveMachineInstrFromMaps(MI); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInsertVSETVLI.cpp56 const LiveIntervals *LIS) { in getVNInfoFromReg() argument
58 if (!LIS) in getVNInfoFromReg()
60 auto &LI = LIS->getInterval(Reg); in getVNInfoFromReg()
61 SlotIndex SI = LIS->getSlotIndexes()->getInstructionIndex(MI); in getVNInfoFromReg()
558 const MachineInstr *getAVLDefMI(const LiveIntervals *LIS) const { in getAVLDefMI()
560 if (!LIS || getAVLVNInfo()->isPHIDef()) in getAVLDefMI()
562 auto *MI = LIS->getInstructionFromIndex(getAVLVNInfo()->def); in getAVLDefMI()
586 bool hasNonZeroAVL(const LiveIntervals *LIS) const { in hasNonZeroAVL()
590 if (auto *DefMI = getAVLDefMI(LIS)) in hasNonZeroAVL()
599 const LiveIntervals *LIS) const { in hasEquallyZeroAVL()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp40 LiveInterval &LI = LIS.createEmptyInterval(VReg); in createEmptyIntervalFrom()
47 LiveInterval &OldLI = LIS.getInterval(OldReg); in createEmptyIntervalFrom()
48 VNInfo::Allocator &Alloc = LIS.getVNInfoAllocator(); in createEmptyIntervalFrom()
67 LIS.getInterval(VReg).markNotSpillable(); in createFrom()
86 LiveInterval &OrigLI = LIS.getInterval(Original); in scanRemattable()
90 MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def); in scanRemattable()
123 LiveInterval &li = LIS.getInterval(MO.getReg()); in allUsesAvailableAt()
169 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt()
194 return LIS.ReplaceMachineInstrInMaps(*ReplaceIndexMI, *MI).getRegSlot(); in rematerializeAt()
195 return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot(); in rematerializeAt()
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H A DSplitKit.cpp63 : LIS(lis), LastInsertPoint(BBNum) {} in InsertPointAnalysis()
70 SlotIndex MBBEnd = LIS.getMBBEndIdx(&MBB); in computeLastInsertPoint()
89 LIP.first = LIS.getInstructionIndex(*FirstTerm); in computeLastInsertPoint()
102 LIP.second = LIS.getInstructionIndex(MI); in computeLastInsertPoint()
114 return LIS.isLiveInToMBB(CurLI, EHPad); in computeLastInsertPoint()
126 if (auto *I = LIS.getInstructionFromIndex(LIP.second)) in computeLastInsertPoint()
145 if (LIP == LIS.getMBBEndIdx(&MBB)) in getLastInsertPointIter()
147 return LIS.getInstructionFromIndex(LIP); in getLastInsertPointIter()
156 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis), Loops(mli), in SplitAnalysis()
180 UseSlots.push_back(LIS.getInstructionIndex(*MO.getParent()).getRegSlot()); in analyzeUses()
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H A DRenameIndependentSubregs.cpp49 RenameIndependentSubregs(LiveIntervals *LIS) : LIS(LIS) {} in RenameIndependentSubregs() argument
59 SubRangeInfo(LiveIntervals &LIS, LiveInterval::SubRange &SR, in SubRangeInfo()
61 : ConEQ(LIS), SR(&SR), Index(Index) {} in SubRangeInfo()
91 LiveIntervals *LIS = nullptr; member in __anon60dd69b50111::RenameIndependentSubregs
149 LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg); in INITIALIZE_PASS_DEPENDENCY()
168 SubRangeInfos.push_back(SubRangeInfo(*LIS, SR, NumComponents)); in findComponents()
195 SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent()); in findComponents()
229 SlotIndex Pos = LIS->getInstructionIndex(*MI); in rewriteOperands()
277 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator(); in distribute()
309 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator(); in computeMainRangesFixFlags()
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H A DPHIElimination.cpp72 LiveIntervals *LIS = nullptr; member in __anonf60509ee0111::PHIEliminationImpl
127 LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr; in PHIEliminationImpl()
134 LIS(AM.getCachedResult<LiveIntervalsAnalysis>(MF)), in PHIEliminationImpl()
220 if (!DisableEdgeSplitting && (LV || LIS)) { in run()
259 if (LV || LIS) in run()
270 if (LIS) in run()
271 LIS->RemoveMachineInstrFromMaps(*DefMI); in run()
278 if (LIS) in run()
279 LIS->RemoveMachineInstrFromMaps(*I.first); in run()
469 if (LIS) { in LowerPHINode()
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H A DRegisterCoalescer.cpp132 LiveIntervals *LIS = nullptr; member in __anonf9586a8a0111::RegisterCoalescer
347 if (LIS->shrinkToUses(LI, Dead)) { in shrinkToUses()
351 LIS->splitSeparateComponents(*LI, SplitLIs); in shrinkToUses()
361 LIS->RemoveMachineInstrFromMaps(*MI); in deleteInstr()
383 RegisterCoalescer(LiveIntervals *LIS, SlotIndexes *SI, in RegisterCoalescer() argument
385 : LIS(LIS), SI(SI), Loops(Loops) {} in RegisterCoalescer()
614 LiveRangeEdit(nullptr, NewRegs, *MF, *LIS, nullptr, this) in eliminateDeadDefs()
629 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg()); in adjustCopiesBackFrom()
631 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg()); in adjustCopiesBackFrom()
632 SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot(); in adjustCopiesBackFrom()
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H A DLiveDebugVariables.cpp314 ArrayRef<unsigned> SpillOffsets, LiveIntervals &LIS,
322 LiveIntervals &LIS);
453 LiveIntervals &LIS);
469 MachineRegisterInfo &MRI, LiveIntervals &LIS);
474 LiveIntervals &LIS, LexicalScopes &LS);
479 LiveIntervals &LIS);
490 void emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
511 LiveIntervals &LIS, const TargetInstrInfo &TII,
526 void emitDebugLabel(LiveIntervals &LIS, const TargetInstrInfo &TII,
548 LiveIntervals *LIS; member in llvm::LiveDebugVariables::LDVImpl
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H A DInlineSpiller.cpp81 LiveIntervals &LIS; member in __anon2f89086e0111::HoistSpillHelper
133 : MF(mf), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT), in HoistSpillHelper()
136 IPA(LIS, mf.getNumBlockIDs()) {} in HoistSpillHelper()
147 LiveIntervals &LIS; member in __anon2f89086e0111::InlineSpiller
191 : MF(MF), LIS(Analyses.LIS), LSS(Analyses.LSS), VRM(VRM), in InlineSpiller()
309 static void getVDefInterval(const MachineInstr &MI, LiveIntervals &LIS) { in getVDefInterval() argument
312 LIS.getInterval(MO.getReg()); in getVDefInterval()
332 if (!LIS.intervalIsInOneMBB(SnipLI)) in isSnippet()
339 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); in isSnippet()
398 LiveInterval &SnipLI = LIS.getInterval(SnipReg); in collectRegsToSpill()
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H A DRegAllocPBQP.cpp159 void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
166 MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
178 void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
181 void postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS);
190 LiveIntervals &LIS = G.getMetadata().LIS; in apply() local
198 LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight(); in apply()
307 LiveIntervals &LIS = G.getMetadata().LIS; in apply() local
331 LiveInterval &LI = LIS.getInterval(VReg); in apply()
526 PBQPVirtRegAuxInfo(MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM, in PBQPVirtRegAuxInfo() argument
529 : VirtRegAuxInfo(MF, LIS, VRM, Loops, MBFI) {} in PBQPVirtRegAuxInfo()
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H A DTwoAddressInstructionPass.cpp99 LiveIntervals *LIS = nullptr; member in __anon97cd436d0111::TwoAddressInstructionImpl
273 LIS(MFAM.getCachedResult<LiveIntervalsAnalysis>(Func)), in INITIALIZE_PASS_DEPENDENCY()
289 LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr; in TwoAddressInstructionImpl()
388 SlotIndex useIdx = LIS->getInstructionIndex(*MI); in isPlainlyKilled()
404 if (LIS && !LIS->isNotInMIMap(*MI)) { in isPlainlyKilled()
406 return isPlainlyKilled(MI, LIS->getInterval(Reg)); in isPlainlyKilled()
411 return isPlainlyKilled(MI, LIS->getRegUnit(U)); in isPlainlyKilled()
793 MachineInstr *NewMI = TII->convertToThreeAddress(*mi, LV, LIS); in convertInstTo3Addr()
914 if (!LV && !LIS) in rescheduleMIBelowKill()
924 if (LIS) { in rescheduleMIBelowKill()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp59 LiveIntervals *LIS; member
101 SlotIndex FMAIdx = LIS->getInstructionIndex(MI); in processBlock()
104 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn(); in processBlock()
110 MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->def); in processBlock()
184 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
188 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
205 !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx)) in processBlock()
273 LiveInterval &FMAInt = LIS->getInterval(OldFMAReg); in processBlock()
289 LIS->removeInterval(KilledProdReg); in processBlock()
291 LIS->createAndComputeVirtRegInterval(KilledProdReg); in processBlock()
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