1 /* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Cavium, Inc. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* \file cn23xx_pf_regs.h 35 * \brief Host Driver: Register Address and Register Mask values for 36 * CN23XX devices. 37 */ 38 39 #ifndef __CN23XX_PF_REGS_H__ 40 #define __CN23XX_PF_REGS_H__ 41 42 #define LIO_CN23XX_CFG_PCIE_DEVCTL 0x78 43 #define LIO_CN23XX_CFG_PCIE_UNCORRECT_ERR_MASK 0x108 44 #define LIO_CN23XX_CFG_PCIE_CORRECT_ERR_STATUS 0x110 45 #define LIO_CN23XX_CFG_PCIE_DEVCTL_MASK 0x00040000 46 47 #define LIO_CN23XX_PCIE_SRIOV_FDL 0x188 48 #define LIO_CN23XX_PCIE_SRIOV_FDL_BIT_POS 0x10 49 #define LIO_CN23XX_PCIE_SRIOV_FDL_MASK 0xFF 50 51 /* ############## BAR0 Registers ################ */ 52 53 #define LIO_CN23XX_SLI_CTL_PORT_START 0x286E0 54 #define LIO_CN23XX_PORT_OFFSET 0x10 55 56 #define LIO_CN23XX_SLI_CTL_PORT(p) \ 57 (LIO_CN23XX_SLI_CTL_PORT_START + \ 58 ((p) * LIO_CN23XX_PORT_OFFSET)) 59 60 /* 2 scatch registers (64-bit) */ 61 #define LIO_CN23XX_SLI_WINDOW_CTL 0x282E0 62 #define LIO_CN23XX_SLI_SCRATCH1 0x283C0 63 #define LIO_CN23XX_SLI_SCRATCH2 0x283D0 64 #define LIO_CN23XX_SLI_WINDOW_CTL_DEFAULT 0x200000ULL 65 66 /* 1 registers (64-bit) - SLI_CTL_STATUS */ 67 #define LIO_CN23XX_SLI_CTL_STATUS 0x28570 68 69 /* 70 * SLI Packet Input Jabber Register (64 bit register) 71 * <31:0> for Byte count for limiting sizes of packet sizes 72 * that are allowed for sli packet inbound packets. 73 * the default value is 0xFA00(=64000). 74 */ 75 #define LIO_CN23XX_SLI_PKT_IN_JABBER 0x29170 76 77 #define LIO_CN23XX_SLI_WIN_WR_ADDR_LO 0x20000 78 #define LIO_CN23XX_SLI_WIN_WR_ADDR64 LIO_CN23XX_SLI_WIN_WR_ADDR_LO 79 80 #define LIO_CN23XX_SLI_WIN_RD_ADDR_LO 0x20010 81 #define LIO_CN23XX_SLI_WIN_RD_ADDR_HI 0x20014 82 #define LIO_CN23XX_SLI_WIN_RD_ADDR64 LIO_CN23XX_SLI_WIN_RD_ADDR_LO 83 84 #define LIO_CN23XX_SLI_WIN_WR_DATA_LO 0x20020 85 #define LIO_CN23XX_SLI_WIN_WR_DATA_HI 0x20024 86 #define LIO_CN23XX_SLI_WIN_WR_DATA64 LIO_CN23XX_SLI_WIN_WR_DATA_LO 87 88 #define LIO_CN23XX_SLI_WIN_RD_DATA_LO 0x20040 89 #define LIO_CN23XX_SLI_WIN_RD_DATA_HI 0x20044 90 #define LIO_CN23XX_SLI_WIN_RD_DATA64 LIO_CN23XX_SLI_WIN_RD_DATA_LO 91 92 #define LIO_CN23XX_SLI_WIN_WR_MASK_REG 0x20030 93 #define LIO_CN23XX_SLI_MAC_CREDIT_CNT 0x23D70 94 95 /* 96 * 4 registers (64-bit) for mapping IOQs to MACs(PEMs)- 97 * SLI_PKT_MAC(0..3)_PF(0..1)_RINFO 98 */ 99 #define LIO_CN23XX_SLI_PKT_MAC_RINFO_START64 0x29030 100 101 /*1 register (64-bit) to determine whether IOQs are in reset. */ 102 #define LIO_CN23XX_SLI_PKT_IOQ_RING_RST 0x291E0 103 104 /* Each Input Queue register is at a 16-byte Offset in BAR0 */ 105 #define LIO_CN23XX_IQ_OFFSET 0x20000 106 107 #define LIO_CN23XX_MAC_RINFO_OFFSET 0x20 108 #define LIO_CN23XX_PF_RINFO_OFFSET 0x10 109 110 #define LIO_CN23XX_SLI_PKT_MAC_RINFO64(mac, pf) \ 111 (LIO_CN23XX_SLI_PKT_MAC_RINFO_START64 + \ 112 ((mac) * LIO_CN23XX_MAC_RINFO_OFFSET) + \ 113 ((pf) * LIO_CN23XX_PF_RINFO_OFFSET)) 114 115 /* mask for total rings, setting TRS to base */ 116 #define LIO_CN23XX_PKT_MAC_CTL_RINFO_TRS BIT_ULL(16) 117 118 /* Starting bit of the TRS field in LIO_CN23XX_SLI_PKT_MAC_RINFO64 register */ 119 #define LIO_CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS 16 120 121 /*###################### REQUEST QUEUE #########################*/ 122 123 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */ 124 #define LIO_CN23XX_SLI_PKT_IN_DONE_CNTS_START64 0x10040 125 126 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */ 127 #define LIO_CN23XX_SLI_PKT_INSTR_BADDR_START64 0x10010 128 129 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */ 130 #define LIO_CN23XX_SLI_PKT_INSTR_BADDR_DBELL_START 0x10020 131 132 /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */ 133 #define LIO_CN23XX_SLI_PKT_INSTR_FIFO_RSIZE_START 0x10030 134 135 /* 136 * 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data & 137 * gather list fetches. SLI_PKT(0..63)_INPUT_CONTROL. 138 */ 139 #define LIO_CN23XX_SLI_PKT_INPUT_CONTROL_START64 0x10000 140 141 /*------- Request Queue Macros ---------*/ 142 #define LIO_CN23XX_SLI_IQ_PKT_CONTROL64(iq) \ 143 (LIO_CN23XX_SLI_PKT_INPUT_CONTROL_START64 + \ 144 ((iq) * LIO_CN23XX_IQ_OFFSET)) 145 146 #define LIO_CN23XX_SLI_IQ_BASE_ADDR64(iq) \ 147 (LIO_CN23XX_SLI_PKT_INSTR_BADDR_START64 + \ 148 ((iq) * LIO_CN23XX_IQ_OFFSET)) 149 150 #define LIO_CN23XX_SLI_IQ_SIZE(iq) \ 151 (LIO_CN23XX_SLI_PKT_INSTR_FIFO_RSIZE_START + \ 152 ((iq) * LIO_CN23XX_IQ_OFFSET)) 153 154 #define LIO_CN23XX_SLI_IQ_DOORBELL(iq) \ 155 (LIO_CN23XX_SLI_PKT_INSTR_BADDR_DBELL_START + \ 156 ((iq) * LIO_CN23XX_IQ_OFFSET)) 157 158 #define LIO_CN23XX_SLI_IQ_INSTR_COUNT64(iq) \ 159 (LIO_CN23XX_SLI_PKT_IN_DONE_CNTS_START64 + \ 160 ((iq) * LIO_CN23XX_IQ_OFFSET)) 161 162 /*------------------ Masks ----------------*/ 163 #define LIO_CN23XX_PKT_INPUT_CTL_VF_NUM BIT_ULL(32) 164 #define LIO_CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29) 165 /* 166 * Number of instructions to be read in one MAC read request. 167 * setting to Max value(4) 168 */ 169 #define LIO_CN23XX_PKT_INPUT_CTL_RDSIZE (3 << 25) 170 #define LIO_CN23XX_PKT_INPUT_CTL_IS_64B BIT(24) 171 #define LIO_CN23XX_PKT_INPUT_CTL_RST BIT(23) 172 #define LIO_CN23XX_PKT_INPUT_CTL_QUIET BIT(28) 173 #define LIO_CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22) 174 #define LIO_CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP BIT(6) 175 #define LIO_CN23XX_PKT_INPUT_CTL_USE_CSR BIT(4) 176 #define LIO_CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP (2) 177 178 #define LIO_CN23XX_PKT_INPUT_CTL_PF_NUM_POS (45) 179 /* These bits[43:32] select the function number within the PF */ 180 #define LIO_CN23XX_PKT_INPUT_CTL_MAC_NUM_POS (29) 181 #define LIO_CN23XX_PKT_IN_DONE_WMARK_MASK (0xFFFFULL) 182 #define LIO_CN23XX_PKT_IN_DONE_WMARK_BIT_POS (32) 183 #define LIO_CN23XX_PKT_IN_DONE_CNT_MASK 0x00000000FFFFFFFFULL 184 185 #if BYTE_ORDER == LITTLE_ENDIAN 186 #define LIO_CN23XX_PKT_INPUT_CTL_MASK \ 187 (LIO_CN23XX_PKT_INPUT_CTL_RDSIZE | \ 188 LIO_CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP | \ 189 LIO_CN23XX_PKT_INPUT_CTL_USE_CSR) 190 #else /* BYTE_ORDER != LITTLE_ENDIAN */ 191 #define LIO_CN23XX_PKT_INPUT_CTL_MASK \ 192 (LIO_CN23XX_PKT_INPUT_CTL_RDSIZE | \ 193 LIO_CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP | \ 194 LIO_CN23XX_PKT_INPUT_CTL_USE_CSR | \ 195 LIO_CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP) 196 #endif /* BYTE_ORDER == LITTLE_ENDIAN */ 197 198 /*############################ OUTPUT QUEUE #########################*/ 199 200 /* 64 registers for Output queue control - SLI_PKT(0..63)_OUTPUT_CONTROL */ 201 #define LIO_CN23XX_SLI_PKT_OUTPUT_CONTROL_START 0x10050 202 203 /* 64 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */ 204 #define LIO_CN23XX_SLI_PKT_OUT_SIZE 0x10060 205 206 /* 64 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */ 207 #define LIO_CN23XX_SLI_SLIST_BADDR_START64 0x10070 208 209 /* 64 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */ 210 #define LIO_CN23XX_SLI_PKT_SLIST_BAOFF_DBELL_START 0x10080 211 212 /* 64 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */ 213 #define LIO_CN23XX_SLI_PKT_SLIST_FIFO_RSIZE_START 0x10090 214 215 /* 64 registers for Output Queue Packet Count - SLI_PKT0_CNTS */ 216 #define LIO_CN23XX_SLI_PKT_CNTS_START 0x100B0 217 218 /* 64 registers for Output Queue INT Levels - SLI_PKT0_INT_LEVELS */ 219 #define LIO_CN23XX_SLI_PKT_INT_LEVELS_START64 0x100A0 220 221 /* Each Output Queue register is at a 16-byte Offset in BAR0 */ 222 #define LIO_CN23XX_OQ_OFFSET 0x20000 223 224 /* 1 (64-bit register) for Output Queue backpressure across all rings. */ 225 #define LIO_CN23XX_SLI_OQ_WMARK 0x29180 226 227 /* Global pkt control register */ 228 #define LIO_CN23XX_SLI_GBL_CONTROL 0x29210 229 230 /* Backpressure enable register for PF0 */ 231 #define LIO_CN23XX_SLI_OUT_BP_EN_W1S 0x29260 232 233 /* Backpressure enable register for PF1 */ 234 #define LIO_CN23XX_SLI_OUT_BP_EN2_W1S 0x29270 235 236 /*------- Output Queue Macros ---------*/ 237 238 #define LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq) \ 239 (LIO_CN23XX_SLI_PKT_OUTPUT_CONTROL_START + \ 240 ((oq) * LIO_CN23XX_OQ_OFFSET)) 241 242 #define LIO_CN23XX_SLI_OQ_BASE_ADDR64(oq) \ 243 (LIO_CN23XX_SLI_SLIST_BADDR_START64 + \ 244 ((oq) * LIO_CN23XX_OQ_OFFSET)) 245 246 #define LIO_CN23XX_SLI_OQ_SIZE(oq) \ 247 (LIO_CN23XX_SLI_PKT_SLIST_FIFO_RSIZE_START + \ 248 ((oq) * LIO_CN23XX_OQ_OFFSET)) 249 250 #define LIO_CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq) \ 251 (LIO_CN23XX_SLI_PKT_OUT_SIZE + \ 252 ((oq) * LIO_CN23XX_OQ_OFFSET)) 253 254 #define LIO_CN23XX_SLI_OQ_PKTS_SENT(oq) \ 255 (LIO_CN23XX_SLI_PKT_CNTS_START + \ 256 ((oq) * LIO_CN23XX_OQ_OFFSET)) 257 258 #define LIO_CN23XX_SLI_OQ_PKTS_CREDIT(oq) \ 259 (LIO_CN23XX_SLI_PKT_SLIST_BAOFF_DBELL_START + \ 260 ((oq) * LIO_CN23XX_OQ_OFFSET)) 261 262 #define LIO_CN23XX_SLI_OQ_PKT_INT_LEVELS(oq) \ 263 (LIO_CN23XX_SLI_PKT_INT_LEVELS_START64 + \ 264 ((oq) * LIO_CN23XX_OQ_OFFSET)) 265 266 /*------------------ Masks ----------------*/ 267 #define LIO_CN23XX_PKT_OUTPUT_CTL_TENB BIT(13) 268 #define LIO_CN23XX_PKT_OUTPUT_CTL_CENB BIT(12) 269 #define LIO_CN23XX_PKT_OUTPUT_CTL_IPTR BIT(11) 270 #define LIO_CN23XX_PKT_OUTPUT_CTL_ES BIT(9) 271 #define LIO_CN23XX_PKT_OUTPUT_CTL_NSR BIT(8) 272 #define LIO_CN23XX_PKT_OUTPUT_CTL_ROR BIT(7) 273 #define LIO_CN23XX_PKT_OUTPUT_CTL_DPTR BIT(6) 274 #define LIO_CN23XX_PKT_OUTPUT_CTL_BMODE BIT(5) 275 #define LIO_CN23XX_PKT_OUTPUT_CTL_ES_P BIT(3) 276 #define LIO_CN23XX_PKT_OUTPUT_CTL_NSR_P BIT(2) 277 #define LIO_CN23XX_PKT_OUTPUT_CTL_ROR_P BIT(1) 278 #define LIO_CN23XX_PKT_OUTPUT_CTL_RING_ENB BIT(0) 279 280 /*######################## MSIX TABLE #########################*/ 281 282 #define LIO_CN23XX_MSIX_TABLE_ADDR_START 0x0 283 #define CN23XX_MSIX_TABLE_DATA_START 0x8 284 #define CN23XX_MSIX_TABLE_SIZE 0x10 285 286 #define CN23XX_MSIX_TABLE_ADDR(idx) \ 287 (LIO_CN23XX_MSIX_TABLE_ADDR_START + \ 288 ((idx) * LIO_CN23XX_MSIX_TABLE_SIZE)) 289 290 #define CN23XX_MSIX_TABLE_DATA(idx) \ 291 (LIO_CN23XX_MSIX_TABLE_DATA_START + \ 292 ((idx) * LIO_CN23XX_MSIX_TABLE_SIZE)) 293 294 /*######################## INTERRUPTS #########################*/ 295 #define LIO_CN23XX_MAC_INT_OFFSET 0x20 296 #define LIO_CN23XX_PF_INT_OFFSET 0x10 297 298 /* 1 register (64-bit) for Interrupt Summary */ 299 #define LIO_CN23XX_SLI_INT_SUM64 0x27000 300 301 /* 4 registers (64-bit) for Interrupt Enable for each Port */ 302 #define LIO_CN23XX_SLI_INT_ENB64 0x27080 303 304 #define LIO_CN23XX_SLI_MAC_PF_INT_SUM64(mac, pf) \ 305 (LIO_CN23XX_SLI_INT_SUM64 + \ 306 ((mac) * LIO_CN23XX_MAC_INT_OFFSET) + \ 307 ((pf) * LIO_CN23XX_PF_INT_OFFSET)) 308 309 #define LIO_CN23XX_SLI_MAC_PF_INT_ENB64(mac, pf) \ 310 (LIO_CN23XX_SLI_INT_ENB64 + \ 311 ((mac) * LIO_CN23XX_MAC_INT_OFFSET) + \ 312 ((pf) * LIO_CN23XX_PF_INT_OFFSET)) 313 314 /* 1 register (64-bit) to indicate which Output Queue reached pkt threshold */ 315 #define LIO_CN23XX_SLI_PKT_CNT_INT 0x29130 316 317 /* 1 register (64-bit) to indicate which Output Queue reached time threshold */ 318 #define LIO_CN23XX_SLI_PKT_TIME_INT 0x29140 319 320 /*------------------ Interrupt Masks ----------------*/ 321 322 #define LIO_CN23XX_INTR_PO_INT BIT_ULL(63) 323 #define LIO_CN23XX_INTR_PI_INT BIT_ULL(62) 324 #define LIO_CN23XX_INTR_RESEND BIT_ULL(60) 325 326 #define LIO_CN23XX_INTR_CINT_ENB BIT_ULL(48) 327 328 #define LIO_CN23XX_INTR_MIO_INT BIT(1) 329 #define LIO_CN23XX_INTR_PKT_TIME BIT(5) 330 #define LIO_CN23XX_INTR_M0UPB0_ERR BIT(8) 331 #define LIO_CN23XX_INTR_M0UPWI_ERR BIT(9) 332 #define LIO_CN23XX_INTR_M0UNB0_ERR BIT(10) 333 #define LIO_CN23XX_INTR_M0UNWI_ERR BIT(11) 334 335 #define LIO_CN23XX_INTR_DMA0_FORCE BIT_ULL(32) 336 #define LIO_CN23XX_INTR_DMA1_FORCE BIT_ULL(33) 337 338 #define LIO_CN23XX_INTR_DMA0_TIME BIT_ULL(36) 339 #define LIO_CN23XX_INTR_DMA1_TIME BIT_ULL(37) 340 341 #define LIO_CN23XX_INTR_DMAPF_ERR BIT_ULL(59) 342 343 #define LIO_CN23XX_INTR_PKTPF_ERR BIT_ULL(61) 344 #define LIO_CN23XX_INTR_PPPF_ERR BIT_ULL(63) 345 346 #define LIO_CN23XX_INTR_DMA0_DATA (LIO_CN23XX_INTR_DMA0_TIME) 347 #define LIO_CN23XX_INTR_DMA1_DATA (LIO_CN23XX_INTR_DMA1_TIME) 348 349 #define LIO_CN23XX_INTR_DMA_DATA \ 350 (LIO_CN23XX_INTR_DMA0_DATA | LIO_CN23XX_INTR_DMA1_DATA) 351 352 /* By fault only TIME based */ 353 #define LIO_CN23XX_INTR_PKT_DATA (LIO_CN23XX_INTR_PKT_TIME) 354 355 /* Sum of interrupts for error events */ 356 #define LIO_CN23XX_INTR_ERR \ 357 (LIO_CN23XX_INTR_M0UPB0_ERR | \ 358 LIO_CN23XX_INTR_M0UPWI_ERR | \ 359 LIO_CN23XX_INTR_M0UNB0_ERR | \ 360 LIO_CN23XX_INTR_M0UNWI_ERR | \ 361 LIO_CN23XX_INTR_DMAPF_ERR | \ 362 LIO_CN23XX_INTR_PKTPF_ERR | \ 363 LIO_CN23XX_INTR_PPPF_ERR) 364 365 /* Programmed Mask for Interrupt Sum */ 366 #define LIO_CN23XX_INTR_MASK \ 367 (LIO_CN23XX_INTR_DMA_DATA | \ 368 LIO_CN23XX_INTR_DMA0_FORCE | \ 369 LIO_CN23XX_INTR_DMA1_FORCE | \ 370 LIO_CN23XX_INTR_MIO_INT | \ 371 LIO_CN23XX_INTR_ERR) 372 373 /* 4 Registers (64 - bit) */ 374 #define LIO_CN23XX_SLI_S2M_PORT_CTL_START 0x23D80 375 #define LIO_CN23XX_SLI_S2M_PORTX_CTL(port) \ 376 (LIO_CN23XX_SLI_S2M_PORT_CTL_START + \ 377 ((port) * 0x10)) 378 379 #define LIO_CN23XX_SLI_MAC_NUMBER 0x20050 380 381 /* 382 * PEM(0..3)_BAR1_INDEX(0..15)address is defined as 383 * addr = (0x00011800C0000100 |port <<24 |idx <<3 ) 384 * Here, port is PEM(0..3) & idx is INDEX(0..15) 385 */ 386 #define LIO_CN23XX_PEM_BAR1_INDEX_START 0x00011800C0000100ULL 387 #define LIO_CN23XX_PEM_OFFSET 24 388 #define LIO_CN23XX_BAR1_INDEX_OFFSET 3 389 390 #define LIO_CN23XX_PEM_BAR1_INDEX_REG(port, idx) \ 391 (LIO_CN23XX_PEM_BAR1_INDEX_START + \ 392 ((port) << LIO_CN23XX_PEM_OFFSET) + \ 393 ((idx) << LIO_CN23XX_BAR1_INDEX_OFFSET)) 394 395 /*############################ DPI #########################*/ 396 /* 4 Registers (64-bit) */ 397 #define LIO_CN23XX_DPI_SLI_PRT_CFG_START 0x0001df0000000900ULL 398 #define LIO_CN23XX_DPI_SLI_PRTX_CFG(port) \ 399 ((IO_CN23XX_DPI_SLI_PRT_CFG_START + \ 400 ((port) * 0x8)) 401 402 /*############################ RST #########################*/ 403 404 #define LIO_CN23XX_RST_BOOT 0x0001180006001600ULL 405 #define LIO_CN23XX_RST_SOFT_RST 0x0001180006001680ULL 406 407 #define LIO_CN23XX_LMC0_RESET_CTL 0x0001180088000180ULL 408 #define LIO_CN23XX_LMC0_RESET_CTL_DDR3RST_MASK 0x0000000000000001ULL 409 410 #endif /* __CN23XX_PF_REGS_H__ */ 411