| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1409 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); in matchIsFiniteTest() local
1413 if (!matchIsNotNaN(PredL, LHS0, LHS1) || in matchIsFiniteTest()
1423 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); in foldLogicOfFCmps() local
1427 if (LHS0 == RHS1 && RHS0 == LHS1) { in foldLogicOfFCmps()
1447 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldLogicOfFCmps()
1454 return getFCmpValue(NewPred, LHS0, LHS1, Builder, in foldLogicOfFCmps()
1468 if (match(LHS1, m_PosZeroFP()) && match(RHS1, m_PosZeroFP())) { in foldLogicOfFCmps()
1498 fcmpToClassTest(PredL, *LHS->getFunction(), LHS0, LHS1); in foldLogicOfFCmps()
1518 match(LHS1, m_APFloatAllowPoison(LHSC)) && in foldLogicOfFCmps()
3341 Value *LHS1 = LHS->getOperand(1), *RHS1 = RHS->getOperand(1); in foldAndOrOfICmps() local
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LICM.cpp | 2454 Value *LHS1, *LHS2, *RHS1, *RHS2; in hoistMinMax() local
2455 if (!MatchICmpAgainstInvariant(Cond1, P1, LHS1, RHS1) || in hoistMinMax()
2459 if (!MatchingPred || LHS1 != LHS2) in hoistMinMax()
2489 Value *NewCond = Builder.CreateICmp(P, LHS1, NewRHS); in hoistMinMax()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 759 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, in getAVRCmp() local
787 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp); in getAVRCmp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 7511 Register LHS1 = Cmp1->getRHSReg(); in tryFoldLogicOfFCmps() local
7515 if (LHS0 == RHS1 && LHS1 == RHS0) { in tryFoldLogicOfFCmps()
7521 if (LHS0 == RHS0 && LHS1 == RHS1) { in tryFoldLogicOfFCmps()
7542 auto Cmp = B.buildFCmp(Pred, CmpTy, LHS0, LHS1, Flags); in tryFoldLogicOfFCmps()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1817 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); in simplifyAndOrOfFCmps() local
1832 match(LHS1, m_PosZeroFP())) in simplifyAndOrOfFCmps()
1846 if ((match(LHS0, AbsOrSelfRHS0) || match(LHS1, AbsOrSelfRHS0)) && in simplifyAndOrOfFCmps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1115 auto *LHS1 = dyn_cast<ConstantSDNode>(LHS.getOperand(1)); in isDesirableToCommuteWithShift() local
1116 return LHS0 && LHS1 && RHSLd && LHS0->getExtensionType() == ISD::ZEXTLOAD && in isDesirableToCommuteWithShift()
1117 LHS1->getAPIntValue() == LHS0->getMemoryVT().getScalarSizeInBits() && in isDesirableToCommuteWithShift()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6549 SDValue LHS1 = LHS->getOperand(1); in foldAndOrOfSETCC() local
6553 auto *LHS1C = isConstOrConstSplat(LHS1); in foldAndOrOfSETCC()
6591 Operand1 = LHS1; in foldAndOrOfSETCC()
6594 } else if (LHS1 == RHS1) { in foldAndOrOfSETCC()
6595 CommonValue = LHS1; in foldAndOrOfSETCC()
6604 Operand1 = LHS1; in foldAndOrOfSETCC()
6607 } else if (RHS0 == LHS1) { in foldAndOrOfSETCC()
6608 CommonValue = LHS1; in foldAndOrOfSETCC()
6646 if (LHS0 == LHS1 && RHS0 == RHS1 && CCL == CCR && in foldAndOrOfSETCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5776 SDValue LHS1, LHS2; in OptimizeVFPBrcond() local
5778 expandf64Toi32(LHS, DAG, LHS1, LHS2); in OptimizeVFPBrcond()
5784 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
12296 Register LHS1 = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
12300 .addReg(LHS1) in EmitInstrWithCustomInserter()
12310 .addReg(LHS1) in EmitInstrWithCustomInserter()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 17973 SDValue LHS1 = LHS.getOperand(1); in performVP_TRUNCATECombine() local
17974 if (!FindAdd(LHS0, LHS1) && !FindAdd(LHS1, LHS0)) in performVP_TRUNCATECombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 23858 SDValue LHS1, LHS2; in splitVSETCC() local
23859 std::tie(LHS1, LHS2) = splitVector(LHS, DAG, dl); in splitVSETCC()
23869 DAG.getNode(ISD::SETCC, dl, LoVT, LHS1, RHS1, CC), in splitVSETCC()
50381 SDValue LHS1 = LHS.getOperand(1); in combineVectorHADDSUB() local
50384 if ((LHS0 == LHS1 || LHS0.isUndef() || LHS1.isUndef()) && in combineVectorHADDSUB()
50388 LHS0.isUndef() ? LHS1 : LHS0, in combineVectorHADDSUB()
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