| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1361 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); in matchIsFiniteTest() local
1365 if (!matchIsNotNaN(PredL, LHS0, LHS1) || in matchIsFiniteTest()
1379 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); in foldLogicOfFCmps() local
1383 if (LHS0 == RHS1 && RHS0 == LHS1) { in foldLogicOfFCmps()
1403 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldLogicOfFCmps()
1415 return getFCmpValue(NewPred, LHS0, LHS1, Builder); in foldLogicOfFCmps()
1428 if (match(LHS1, m_PosZeroFP()) && match(RHS1, m_PosZeroFP())) in foldLogicOfFCmps()
1454 fcmpToClassTest(PredL, *LHS->getFunction(), LHS0, LHS1); in foldLogicOfFCmps()
1474 match(LHS1, m_APFloatAllowPoison(LHSC)) && in foldLogicOfFCmps()
3289 Value *LHS1 = LHS->getOperand(1), *RHS1 = RHS->getOperand(1); in foldAndOrOfICmps() local
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LICM.cpp | 2443 Value *LHS1, *LHS2, *RHS1, *RHS2; in hoistMinMax() local
2444 if (!MatchICmpAgainstInvariant(Cond1, P1, LHS1, RHS1) || in hoistMinMax()
2447 if (P1 != P2 || LHS1 != LHS2) in hoistMinMax()
2475 Value *NewCond = Builder.CreateICmp(P, LHS1, NewRHS); in hoistMinMax()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 813 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, in getAVRCmp() local
841 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp); in getAVRCmp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 7174 Register LHS1 = Cmp1->getRHSReg(); in tryFoldLogicOfFCmps() local
7178 if (LHS0 == RHS1 && LHS1 == RHS0) { in tryFoldLogicOfFCmps()
7184 if (LHS0 == RHS0 && LHS1 == RHS1) { in tryFoldLogicOfFCmps()
7205 auto Cmp = B.buildFCmp(Pred, CmpTy, LHS0, LHS1, Flags); in tryFoldLogicOfFCmps()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1866 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); in simplifyAndOrOfFCmps() local
1879 if ((LHS0 == RHS0 || LHS0 == RHS1) && match(LHS1, m_PosZeroFP())) in simplifyAndOrOfFCmps()
1892 if ((RHS0 == LHS0 || RHS0 == LHS1) && match(RHS1, m_PosZeroFP())) in simplifyAndOrOfFCmps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1052 auto *LHS1 = dyn_cast<ConstantSDNode>(LHS.getOperand(1)); in isDesirableToCommuteWithShift() local
1053 return LHS0 && LHS1 && RHSLd && LHS0->getExtensionType() == ISD::ZEXTLOAD && in isDesirableToCommuteWithShift()
1054 LHS1->getAPIntValue() == LHS0->getMemoryVT().getScalarSizeInBits() && in isDesirableToCommuteWithShift()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6170 SDValue LHS1 = LHS->getOperand(1); in foldAndOrOfSETCC() local
6174 auto *LHS1C = isConstOrConstSplat(LHS1); in foldAndOrOfSETCC()
6212 Operand1 = LHS1; in foldAndOrOfSETCC()
6215 } else if (LHS1 == RHS1) { in foldAndOrOfSETCC()
6216 CommonValue = LHS1; in foldAndOrOfSETCC()
6225 Operand1 = LHS1; in foldAndOrOfSETCC()
6228 } else if (RHS0 == LHS1) { in foldAndOrOfSETCC()
6229 CommonValue = LHS1; in foldAndOrOfSETCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5695 SDValue LHS1, LHS2; in OptimizeVFPBrcond() local
5697 expandf64Toi32(LHS, DAG, LHS1, LHS2); in OptimizeVFPBrcond()
5704 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
12233 Register LHS1 = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
12237 .addReg(LHS1) in EmitInstrWithCustomInserter()
12247 .addReg(LHS1) in EmitInstrWithCustomInserter()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 23118 SDValue LHS1, LHS2; in splitIntVSETCC() local
23119 std::tie(LHS1, LHS2) = splitVector(LHS, DAG, dl); in splitIntVSETCC()
23129 DAG.getNode(ISD::SETCC, dl, LoVT, LHS1, RHS1, CC), in splitIntVSETCC()
48626 SDValue LHS1 = LHS.getOperand(1); in combineVectorHADDSUB() local
48629 if ((LHS0 == LHS1 || LHS0.isUndef() || LHS1.isUndef()) && in combineVectorHADDSUB()
48633 LHS0.isUndef() ? LHS1 : LHS0, in combineVectorHADDSUB()
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