| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1361 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); in matchIsFiniteTest() local
1365 if (!matchIsNotNaN(PredL, LHS0, LHS1) || in matchIsFiniteTest()
1379 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); in foldLogicOfFCmps() local
1383 if (LHS0 == RHS1 && RHS0 == LHS1) { in foldLogicOfFCmps()
1403 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldLogicOfFCmps()
1415 return getFCmpValue(NewPred, LHS0, LHS1, Builder); in foldLogicOfFCmps()
1423 if (LHS0->getType() != RHS0->getType()) in foldLogicOfFCmps()
1432 return Builder.CreateFCmp(PredL, LHS0, RHS0); in foldLogicOfFCmps()
1435 if (IsAnd && stripSignOnlyFPOps(LHS0) == stripSignOnlyFPOps(RHS0)) { in foldLogicOfFCmps()
1454 fcmpToClassTest(PredL, *LHS->getFunction(), LHS0, LHS1); in foldLogicOfFCmps()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1866 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); in simplifyAndOrOfFCmps() local
1868 if (LHS0->getType() != RHS0->getType()) in simplifyAndOrOfFCmps()
1879 if ((LHS0 == RHS0 || LHS0 == RHS1) && match(LHS1, m_PosZeroFP())) in simplifyAndOrOfFCmps()
1892 if ((RHS0 == LHS0 || RHS0 == LHS1) && match(RHS1, m_PosZeroFP())) in simplifyAndOrOfFCmps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 811 SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, in getAVRCmp() local
840 Cmp = getAVRCmp(LHS0, RHS0, DAG, DL); in getAVRCmp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 7173 Register LHS0 = Cmp1->getLHSReg(); in tryFoldLogicOfFCmps() local
7178 if (LHS0 == RHS1 && LHS1 == RHS0) { in tryFoldLogicOfFCmps()
7184 if (LHS0 == RHS0 && LHS1 == RHS1) { in tryFoldLogicOfFCmps()
7205 auto Cmp = B.buildFCmp(Pred, CmpTy, LHS0, LHS1, Flags); in tryFoldLogicOfFCmps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1051 auto *LHS0 = dyn_cast<LoadSDNode>(LHS.getOperand(0)); in isDesirableToCommuteWithShift() local
1053 return LHS0 && LHS1 && RHSLd && LHS0->getExtensionType() == ISD::ZEXTLOAD && in isDesirableToCommuteWithShift()
1054 LHS1->getAPIntValue() == LHS0->getMemoryVT().getScalarSizeInBits() && in isDesirableToCommuteWithShift()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6168 SDValue LHS0 = LHS->getOperand(0); in foldAndOrOfSETCC() local
6179 EVT OpVT = LHS0.getValueType(); in foldAndOrOfSETCC()
6210 if (LHS0 == RHS0) { in foldAndOrOfSETCC()
6211 CommonValue = LHS0; in foldAndOrOfSETCC()
6217 Operand1 = LHS0; in foldAndOrOfSETCC()
6223 if (LHS0 == RHS1) { in foldAndOrOfSETCC()
6224 CommonValue = LHS0; in foldAndOrOfSETCC()
6230 Operand1 = LHS0; in foldAndOrOfSETCC()
6272 LHS0 == RHS0 && LHS1C && RHS1C && OpVT.isInteger()) { in foldAndOrOfSETCC()
6280 DAG.doesNodeExist(ISD::ABS, DAG.getVTList(OpVT), {LHS0}))) { in foldAndOrOfSETCC()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 15821 SDValue LHS0 = LHS.getOperand(0); in combine_CC()
15822 if (LHS0.getOpcode() == ISD::AND && in combine_CC()
15823 LHS0.getOperand(1).getOpcode() == ISD::Constant) { in combine_CC()
15824 uint64_t Mask = LHS0.getConstantOperandVal(1); in combine_CC()
15831 LHS = LHS0.getOperand(0); in combine_CC()
15834 DAG.getNode(ISD::SHL, DL, LHS.getValueType(), LHS0.getOperand(0), in combine_CC()
15818 SDValue LHS0 = LHS.getOperand(0); combine_CC() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 48625 SDValue LHS0 = LHS.getOperand(0); in combineVectorHADDSUB() local
48629 if ((LHS0 == LHS1 || LHS0.isUndef() || LHS1.isUndef()) && in combineVectorHADDSUB()
48633 LHS0.isUndef() ? LHS1 : LHS0, in combineVectorHADDSUB()
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