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Searched refs:LD2 (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2373 def : InstRW<[A64FXWrite_LD2_BH], (instregex "^LD2[BH]")>;
2380 def : InstRW<[A64FXWrite_LD2_WD_IMM], (instregex "^LD2[WD]_IMM")>;
2387 def : InstRW<[A64FXWrite_LD2_WD], (instregex "^LD2[WD]$")>;
H A DAArch64SchedA510.td1226 def : InstRW<[CortexA510MCWrite<3, 1, CortexA510UnitLdSt>], (instregex "^LD2[BHWD]_IMM$")>;
1229 def : InstRW<[CortexA510MCWrite<3, 2, CortexA510UnitLdSt>], (instregex "^LD2[BHWD]$")>;
H A DAArch64SchedA320.td1248 def : InstRW<[CortexA320MCWrite<3, 1, CortexA320UnitLdSt>], (instregex "^LD2[BHWD]_IMM$")>;
1251 def : InstRW<[CortexA320MCWrite<3, 2, CortexA320UnitLdSt>], (instregex "^LD2[BHWD]$")>;
H A DAArch64SchedKryoDetails.td1161 (instregex "LD2(i8|i16|i32)$")>;
1167 (instregex "LD2(i8|i16|i32)_POST$")>;
H A DAArch64SchedNeoverseV1.td1867 def : InstRW<[V1Write_8c_2L01_2V01], (instregex "^LD2[BHWD]_IMM$")>;
1871 def : InstRW<[V1Write_9c_2L01_2V01], (instregex "^LD2[BWD]$")>;
H A DAArch64SchedNeoverseN2.td2184 def : InstRW<[N2Write_8c_1L_1V], (instregex "^LD2[BHWD]_IMM$")>;
2187 def : InstRW<[N2Write_9c_1L_1V], (instregex "^LD2[BHWD]$")>;
H A DAArch64SchedNeoverseN3.td2149 def : InstRW<[N3Write_8c_1V_1L], (instregex "^LD2[BHWD]_IMM$")>;
2152 def : InstRW<[N3Write_8c_1V_1L], (instregex "^LD2[BHWD]$")>;
H A DAArch64SchedNeoverseV2.td2678 def : InstRW<[V2Write_8c_2L_2V], (instregex "^LD2[BHWD]_IMM$")>;
2681 def : InstRW<[V2Write_9c_2L_2V_2S], (instregex "^LD2[BHWD]$")>;
H A DAArch64InstrInfo.td8929 defm LD2 : SIMDLd2Multiple<"ld2">;
8991 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
8992 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
8993 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
8994 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
9147 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15633 LoadSDNode *LD2 = cast<LoadSDNode>(NextInput); in combineBVOfConsecutiveLoads() local
15636 if (IsRoundOfExtLoad && LD2->getExtensionType() != ISD::EXTLOAD) in combineBVOfConsecutiveLoads()
15641 if (!DAG.areNonVolatileConsecutiveLoads(LD2, LD1, ElemSize, 1)) in combineBVOfConsecutiveLoads()
15643 if (!DAG.areNonVolatileConsecutiveLoads(LD1, LD2, ElemSize, 1)) in combineBVOfConsecutiveLoads()
15649 InputLoads.push_back(LD2); in combineBVOfConsecutiveLoads()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp16322 auto *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); in CombineConsecutiveLoads() local
16328 std::swap(LD1, LD2); in CombineConsecutiveLoads()
16330 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !ISD::isNON_EXTLoad(LD2) || in CombineConsecutiveLoads()
16331 !LD1->hasOneUse() || !LD2->hasOneUse() || in CombineConsecutiveLoads()
16332 LD1->getAddressSpace() != LD2->getAddressSpace()) in CombineConsecutiveLoads()
16339 DAG.areNonVolatileConsecutiveLoads(LD2, LD1, LD1Bytes, 1) && in CombineConsecutiveLoads()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_neon.td771 def LD2 : WInst<"vld2", "2(c*!)", "QUlQldQdPlQPlmQm">;