| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedKryoDetails.td | 1017 (instregex "LD1(One(v16b|v8h|v4s|v2d)|i64)$")>;
1023 (instregex "LD1(i8|i16|i32)$")>;
1035 (instregex "LD1(One(v16b|v8h|v4s|v2d)|i64)_POST$")>;
1041 (instregex "LD1(i8|i16|i32)_POST$")>;
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| H A D | AArch64InstrInfo.td | 3721 // We must do vector loads with LD1 in big-endian.
3735 // We must do vector loads with LD1 in big-endian.
3833 // We must use LD1 to perform vector loads in big-endian.
3854 // We must use LD1 to perform vector loads in big-endian.
8928 defm LD1 : SIMDLd1Multiple<"ld1">;
8987 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
8988 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
8989 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
8990 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
9056 ValueType VTy, ValueType STy, Instruction LD1>
[all …]
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| H A D | AArch64SchedNeoverseV1.td | 1221 (instregex "^LD1(i|Rv)(8|16|32|64)$",
1828 def : InstRW<[V1Write_6c_1L01], (instregex "^LD1[BHWD]_IMM$",
1832 "^LD1[BWD]$",
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| H A D | AArch64SchedFalkorDetails.td | 781 def : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LD1(i64|Onev(8b|4h|2s|1d|16b|8h|4s|2d))$")>;
783 (instregex "^LD1(i64|Onev(8b|4h|2s|1d|16b|8h|4s|2d))_POST$")>;
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| H A D | AArch64SchedA510.td | 1178 def : InstRW<[CortexA510Write<3, CortexA510UnitLd>], (instregex "^LD1[BHWD]_IMM$",
1183 def : InstRW<[CortexA510Write<3, CortexA510UnitLd>], (instregex "^LD1[BHWD]$",
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| H A D | AArch64SchedA320.td | 1200 def : InstRW<[CortexA320Write<3, CortexA320UnitLdSt>], (instregex "^LD1[BHWD]_IMM$",
1205 def : InstRW<[CortexA320Write<3, CortexA320UnitLdSt>], (instregex "^LD1[BHWD]$",
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| H A D | AArch64SchedNeoverseN2.td | 2136 def : InstRW<[N2Write_6c_1L], (instregex "^LD1[BHWD]_IMM$",
2141 def : InstRW<[N2Write_6c_1L01], (instregex "^LD1[BHWD]$",
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| H A D | AArch64SchedNeoverseN3.td | 2100 def : InstRW<[N3Write_6c_1L], (instregex "^LD1[BHWD]_IMM$",
2106 def : InstRW<[N3Write_6c_1L], (instregex "^LD1[BHWD]$",
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| H A D | AArch64SchedNeoverseN1.td | 845 (instregex "LD1(i|Rv)(8|16|32|64)$",
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| H A D | AArch64SchedNeoverseV2.td | 2632 def : InstRW<[V2Write_6c_1L], (instregex "^LD1[BHWD]_IMM$",
2637 def : InstRW<[V2Write_6c_1L], (instregex "^LD1[BHWD]$",
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| H A D | AArch64InstrFormats.td | 11018 // LD1 instructions have extra "1d" variants.
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 16321 auto *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); in CombineConsecutiveLoads() local
16328 std::swap(LD1, LD2); in CombineConsecutiveLoads()
16330 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !ISD::isNON_EXTLoad(LD2) || in CombineConsecutiveLoads()
16331 !LD1->hasOneUse() || !LD2->hasOneUse() || in CombineConsecutiveLoads()
16332 LD1->getAddressSpace() != LD2->getAddressSpace()) in CombineConsecutiveLoads()
16336 EVT LD1VT = LD1->getValueType(0); in CombineConsecutiveLoads()
16339 DAG.areNonVolatileConsecutiveLoads(LD2, LD1, LD1Bytes, 1) && in CombineConsecutiveLoads()
16341 *LD1->getMemOperand(), &LD1Fast) && LD1Fast) in CombineConsecutiveLoads()
16342 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(), LD1->getBasePtr(), in CombineConsecutiveLoads()
16343 LD1->getPointerInfo(), LD1->getAlign()); in CombineConsecutiveLoads()
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | arm_neon.td | 770 def LD1 : WInst<"vld1", ".(c*!)", "dQdPlQPlmQm">;
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| H A D | arm_sve.td | 1936 defm LD1 : MultiVecLoad<"ld1">;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 15632 LoadSDNode *LD1 = cast<LoadSDNode>(PreviousInput); in combineBVOfConsecutiveLoads() local
15641 if (!DAG.areNonVolatileConsecutiveLoads(LD2, LD1, ElemSize, 1)) in combineBVOfConsecutiveLoads()
15643 if (!DAG.areNonVolatileConsecutiveLoads(LD1, LD2, ElemSize, 1)) in combineBVOfConsecutiveLoads()
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