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Searched refs:LD1 (Results 1 – 13 of 13) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedKryoDetails.td1017 (instregex "LD1(One(v16b|v8h|v4s|v2d)|i64)$")>;
1023 (instregex "LD1(i8|i16|i32)$")>;
1035 (instregex "LD1(One(v16b|v8h|v4s|v2d)|i64)_POST$")>;
1041 (instregex "LD1(i8|i16|i32)_POST$")>;
H A DAArch64InstrInfo.td3371 // We must do vector loads with LD1 in big-endian.
3385 // We must do vector loads with LD1 in big-endian.
3519 // We must use LD1 to perform vector loads in big-endian.
3540 // We must use LD1 to perform vector loads in big-endian.
8379 defm LD1 : SIMDLd1Multiple<"ld1">;
8423 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
8424 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
8425 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
8426 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
8492 ValueType VTy, ValueType STy, Instruction LD1>
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H A DAArch64SchedNeoverseV1.td1108 (instregex "^LD1(i|Rv)(8|16|32|64)$",
1706 def : InstRW<[V1Write_6c_1L01], (instregex "^LD1[BHWD]_IMM$",
1710 "^LD1[BWD]$",
H A DAArch64SchedFalkorDetails.td781 def : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LD1(i64|Onev(8b|4h|2s|1d|16b|8h|4s|2d))$")>;
783 (instregex "^LD1(i64|Onev(8b|4h|2s|1d|16b|8h|4s|2d))_POST$")>;
H A DAArch64SchedA510.td1178 def : InstRW<[CortexA510Write<3, CortexA510UnitLd>], (instregex "^LD1[BHWD]_IMM$",
1183 def : InstRW<[CortexA510Write<3, CortexA510UnitLd>], (instregex "^LD1[BHWD]$",
H A DAArch64SchedNeoverseN2.td2095 def : InstRW<[N2Write_6cyc_1L], (instregex "^LD1[BHWD]_IMM$",
2100 def : InstRW<[N2Write_6cyc_1L01], (instregex "^LD1[BHWD]$",
H A DAArch64SchedNeoverseN1.td845 (instregex "LD1(i|Rv)(8|16|32|64)$",
H A DAArch64SchedNeoverseV2.td2615 def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1[BHWD]_IMM$",
2620 def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1[BHWD]$",
H A DAArch64InstrFormats.td10582 // LD1 instructions have extra "1d" variants.
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp15271 auto *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); in CombineConsecutiveLoads() local
15278 std::swap(LD1, LD2); in CombineConsecutiveLoads()
15280 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !ISD::isNON_EXTLoad(LD2) || in CombineConsecutiveLoads()
15281 !LD1->hasOneUse() || !LD2->hasOneUse() || in CombineConsecutiveLoads()
15282 LD1->getAddressSpace() != LD2->getAddressSpace()) in CombineConsecutiveLoads()
15286 EVT LD1VT = LD1->getValueType(0); in CombineConsecutiveLoads()
15289 DAG.areNonVolatileConsecutiveLoads(LD2, LD1, LD1Bytes, 1) && in CombineConsecutiveLoads()
15291 *LD1->getMemOperand(), &LD1Fast) && LD1Fast) in CombineConsecutiveLoads()
15292 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(), LD1->getBasePtr(), in CombineConsecutiveLoads()
15293 LD1->getPointerInfo(), LD1->getAlign()); in CombineConsecutiveLoads()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_neon.td721 def LD1 : WInst<"vld1", ".(c*!)", "dQdPlQPl">;
H A Darm_sve.td2041 defm LD1 : MultiVecLoad<"ld1">;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp14799 LoadSDNode *LD1 = cast<LoadSDNode>(PreviousInput); in combineBVOfConsecutiveLoads() local
14808 if (!DAG.areNonVolatileConsecutiveLoads(LD2, LD1, ElemSize, 1)) in combineBVOfConsecutiveLoads()
14810 if (!DAG.areNonVolatileConsecutiveLoads(LD1, LD2, ElemSize, 1)) in combineBVOfConsecutiveLoads()