| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LoopPassManager.cpp | 231 LoopStandardAnalysisResults LAR = {AM.getResult<AAManager>(F), in run() local
269 PI.pushBeforeNonSkippedPassCallback([&LAR, &LI](StringRef PassID, Any IR) { in run()
282 assert(L->isRecursivelyLCSSAForm(LAR.DT, LI) && in run()
306 PreservedAnalyses PassPA = Pass->run(*L, LAM, LAR, Updater); in run()
314 if (LAR.MSSA && !PassPA.getChecker<MemorySSAAnalysis>().preserved()) in run()
322 LAR.DT.verify(); in run()
324 LAR.LI.verify(LAR.DT); in run()
326 LAR.SE.verify(); in run()
327 if (LAR in run()
[all...] |
| H A D | LoopVersioningLICM.cpp | 577 LoopStandardAnalysisResults &LAR, in run() argument
579 AliasAnalysis *AA = &LAR.AA; in run()
580 ScalarEvolution *SE = &LAR.SE; in run()
581 DominatorTree *DT = &LAR.DT; in run()
585 LoopAccessInfoManager LAIs(*SE, *AA, *DT, LAR.LI, nullptr, nullptr); in run()
586 if (!LoopVersioningLICM(AA, SE, &ORE, LAIs, LAR.LI, &L).run(DT)) in run()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Scalar/ |
| H A D | LoopVersioningLICM.h | 22 LoopStandardAnalysisResults &LAR, LPMUpdater &U);
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | LoopVectorizationLegality.cpp | 1059 const OptimizationRemarkAnalysis *LAR = LAI->getReport(); in canVectorizeMemory() local
1060 if (LAR) { in canVectorizeMemory()
1063 "loop not vectorized: ", *LAR); in canVectorizeMemory()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 11954 const auto *LAR = cast<SCEVAddRecExpr>(Less); in computeConstantDifference() local
11957 if (LAR->getLoop() != MAR->getLoop()) in computeConstantDifference()
11962 if (!LAR->isAffine() || !MAR->isAffine()) in computeConstantDifference()
11965 if (LAR->getStepRecurrence(*this) != MAR->getStepRecurrence(*this)) in computeConstantDifference()
11968 Less = LAR->getStart(); in computeConstantDifference()
12324 const SCEVAddRecExpr *LAR = dyn_cast<SCEVAddRecExpr>(LHS); in IsKnownPredicateViaAddRecStart() local
12325 if (!LAR) in IsKnownPredicateViaAddRecStart()
12330 if (LAR->getLoop() != RAR->getLoop()) in IsKnownPredicateViaAddRecStart()
12332 if (!LAR->isAffine() || !RAR->isAffine()) in IsKnownPredicateViaAddRecStart()
12335 if (LAR->getStepRecurrence(SE) != RAR->getStepRecurrence(SE)) in IsKnownPredicateViaAddRecStart()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SchedBroadwell.td | 1198 def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
1279 def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
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| H A D | X86SchedSkylakeClient.td | 926 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1281 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
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| H A D | X86SchedHaswell.td | 1385 def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>;
1392 def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm",
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| H A D | X86SchedSkylakeServer.td | 1038 def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1741 def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
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| H A D | X86SchedIceLake.td | 1053 def: InstRW<[ICXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1757 def: InstRW<[ICXWriteResGroup146], (instregex "LAR(16|32|64)rm",
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| H A D | X86ScheduleBdVer2.td | 314 def : InstRW<[PdWriteLARrr], (instregex "LAR(16|32|64)rr",
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| H A D | X86SchedAlderlakeP.td | 1158 def : InstRW<[ADLPWriteResGroup90], (instregex "^LAR(32|64)rr$")>;
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| H A D | X86SchedSapphireRapids.td | 1421 def : InstRW<[SPRWriteResGroup100], (instregex "^LAR(32|64)rr$")>;
|