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Searched refs:K0 (Results 1 – 25 of 60) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankCombiner.cpp83 Register &Val, CstTy &K0, CstTy &K1) const;
98 bool isClampZeroToOne(MachineInstr *K0, MachineInstr *K1) const;
174 CstTy &K0, CstTy &K1) const { in matchMed() argument
185 MMMOpc.Min, m_CommutativeBinOp(MMMOpc.Max, m_Reg(Val), m_Cst(K0)), in matchMed()
189 m_Cst(K0)))); in matchMed()
205 std::optional<ValueAndVReg> K0, K1; in matchIntMinMaxToMed3() local
207 if (!matchMed<GCstAndRegMatch>(MI, MRI, OpcodeTriple, Val, K0, K1)) in matchIntMinMaxToMed3()
210 if (OpcodeTriple.Med == AMDGPU::G_AMDGPU_SMED3 && K0->Value.sgt(K1->Value)) in matchIntMinMaxToMed3()
212 if (OpcodeTriple.Med == AMDGPU::G_AMDGPU_UMED3 && K0->Value.ugt(K1->Value)) in matchIntMinMaxToMed3()
215 MatchInfo = {OpcodeTriple.Med, Val, K0->VReg, K1->VReg}; in matchIntMinMaxToMed3()
[all …]
/freebsd/sys/opencrypto/
H A Drmd160.c59 #define K0 0x00000000U macro
179 R(a, b, c, d, e, F0, K0, 11, 0); in RMD160Transform()
180 R(e, a, b, c, d, F0, K0, 14, 1); in RMD160Transform()
181 R(d, e, a, b, c, F0, K0, 15, 2); in RMD160Transform()
182 R(c, d, e, a, b, F0, K0, 12, 3); in RMD160Transform()
183 R(b, c, d, e, a, F0, K0, 5, 4); in RMD160Transform()
184 R(a, b, c, d, e, F0, K0, 8, 5); in RMD160Transform()
185 R(e, a, b, c, d, F0, K0, 7, 6); in RMD160Transform()
186 R(d, e, a, b, c, F0, K0, 9, 7); in RMD160Transform()
187 R(c, d, e, a, b, F0, K0, 11, 8); in RMD160Transform()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp597 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0) in emitInterruptPrologueStub()
602 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0) in emitInterruptPrologueStub()
603 .addReg(Mips::K0) in emitInterruptPrologueStub()
640 SrcReg = Mips::K0; in emitInterruptPrologueStub()
822 Reg = Mips::K0; in spillCalleeSavedRegisters()
827 BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0) in spillCalleeSavedRegisters()
H A DMipsSEInstrInfo.cpp269 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); in storeRegToStack()
270 SrcReg = Mips::K0; in storeRegToStack()
275 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); in storeRegToStack()
276 SrcReg = Mips::K0; in storeRegToStack()
352 unsigned Reg = Mips::K0; in loadRegFromStack()
H A DMipsRegisterInfo.td114 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
149 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>;
296 K0, K1, GP, SP, FP, RA)>;
316 K0, K1, GP, SP, FP, RA)>;
H A DMipsRegisterInfo.cpp152 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP in getReservedRegs()
/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-bmc-qcom-dc-scm-v1.dts105 /*K0-K7*/ "","","","","","","","",
H A Daspeed-bmc-vegman-n110.dts25 /*K0-K7*/ "","","","","","","","",
H A Daspeed-bmc-vegman-sx20.dts25 /*K0-K7*/ "","","","","","","","",
H A Daspeed-bmc-facebook-minerva.dts608 /*K0-K7*/ "","","","","","","","",
719 /*K0 - K7*/
H A Daspeed-bmc-inventec-transformers.dts281 /*K0-K7*/ "","","","","","","","",
H A Daspeed-bmc-amd-daytonax.dts136 /*K0-K7*/ "","","","","","","","",
H A Daspeed-bmc-facebook-harma.dts576 /*K0-K7*/ "","","","","","","","",
708 /*K0-K3 line 160-167*/
H A Daspeed-bmc-amd-ethanolx.dts133 /*K0-K7*/ "","","","","","","","",
H A Daspeed-bmc-opp-romulus.dts245 /*K0-K7*/ "","","","","","","","",
H A Daspeed-bmc-facebook-greatlakes.dts263 /*K0-K7*/ "","","","","","","","",
H A Daspeed-bmc-opp-nicole.dts230 /*K0-K7*/ "","","","","","","","",
H A Daspeed-bmc-ufispace-ncplite.dts348 /*K0-K7*/ "","","","","","","","",
H A Daspeed-bmc-vegman-rx20.dts53 /*K0-K7*/ "","","","","","","","",
H A Daspeed-bmc-asus-x4tf.dts563 /*K0 80*/ "", "", "", "", "", "", "", "",
H A Daspeed-bmc-facebook-tiogapass.dts145 /*K0-K7*/ "","","","","","","","",
H A Daspeed-bmc-tyan-s8036.dts436 /*K0-K7*/ "","","","","","","","",
H A Daspeed-bmc-inspur-nf5280m6.dts162 /*K0-K7*/ "","","","","","","","",
H A Daspeed-bmc-quanta-s6q.dts99 /*K0 - K7*/ "", "", "", "", "", "", "", "",
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td407 def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, 93, 93]>;
417 [(add K0, K2, K4, K6), (add K1, K3, K5, K7)]>;
826 def VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;}
827 def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;}
828 def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;}
829 def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;}

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