Searched refs:IsVGPR (Results 1 – 5 of 5) sorted by relevance
591 bool IsVGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR; in getMachineOpValue() local592 Op = Idx | (IsVGPR << 8); in getMachineOpValue()606 bool IsVGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR; in getMachineOpValueT16() local607 Op = Idx | (IsVGPR << 8); in getMachineOpValueT16()654 bool IsVGPR = Encoding & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR; in getMachineOpValueT16Lo128() local655 assert((!IsVGPR || isUInt<7>(RegIdx)) && "VGPR0-VGPR127 expected!"); in getMachineOpValueT16Lo128()656 Op = (IsVGPR ? 0x100 : 0) | (IsHi ? 0x80 : 0) | RegIdx; in getMachineOpValueT16Lo128()
337 bool IsVGPR = Imm & (1 << 8); in decodeOperand_VSrcT16_Lo128() local338 if (IsVGPR) { in decodeOperand_VSrcT16_Lo128()353 bool IsVGPR = Imm & (1 << 8); in decodeOperand_VSrcT16() local354 if (IsVGPR) { in decodeOperand_VSrcT16()
2887 const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID; in selectG_GLOBAL_VALUE() local2888 I.setDesc(TII.get(IsVGPR ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32)); in selectG_GLOBAL_VALUE()2889 if (IsVGPR) in selectG_GLOBAL_VALUE()2893 DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, *MRI); in selectG_GLOBAL_VALUE()2908 const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID; in selectG_PTRMASK() local2921 if (!IsVGPR && Ty.getSizeInBits() == 64 && in selectG_PTRMASK()2931 unsigned NewOpc = IsVGPR ? AMDGPU::V_AND_B32_e64 : AMDGPU::S_AND_B32; in selectG_PTRMASK()2933 = IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass; in selectG_PTRMASK()2953 if (!IsVGPR) in selectG_PTRMASK()
1232 bool IsVGPR = TRI->isVGPR(MRI, Reg); in spillVGPRtoAGPR() local1234 if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) { in spillVGPRtoAGPR()1244 unsigned Opc = (IsStore ^ IsVGPR) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64 in spillVGPRtoAGPR()
1776 const bool IsVGPR = TRI->isVectorRegister(*MRI, Op.getReg()); in generateWaitcntInstBefore() local1778 if (IsVGPR) { in generateWaitcntInstBefore()