Searched refs:IsVGPR (Results 1 – 4 of 4) sorted by relevance
608 bool IsVGPR = Enc & AMDGPU::HWEncoding::IS_VGPR; in getMachineOpValueT16() local609 Op = Idx | (IsVGPR << 8); in getMachineOpValueT16()656 bool IsVGPR = Encoding & AMDGPU::HWEncoding::IS_VGPR; in getMachineOpValueT16Lo128() local657 assert((!IsVGPR || isUInt<7>(RegIdx)) && "VGPR0-VGPR127 expected!"); in getMachineOpValueT16Lo128()658 Op = (IsVGPR ? 0x100 : 0) | (IsHi ? 0x80 : 0) | RegIdx; in getMachineOpValueT16Lo128()
3081 const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID; in selectG_GLOBAL_VALUE() local3082 I.setDesc(TII.get(IsVGPR ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32)); in selectG_GLOBAL_VALUE()3083 if (IsVGPR) in selectG_GLOBAL_VALUE()3087 DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, *MRI); in selectG_GLOBAL_VALUE()3102 const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID; in selectG_PTRMASK() local3115 if (!IsVGPR && Ty.getSizeInBits() == 64 && in selectG_PTRMASK()3125 unsigned NewOpc = IsVGPR ? AMDGPU::V_AND_B32_e64 : AMDGPU::S_AND_B32; in selectG_PTRMASK()3127 = IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass; in selectG_PTRMASK()3147 if (!IsVGPR) in selectG_PTRMASK()
1952 const bool IsVGPR = TRI->isVectorRegister(*MRI, Op.getReg()); in generateWaitcntInstBefore() local1953 if (IsVGPR) { in generateWaitcntInstBefore()
1468 bool IsVGPR = TRI->isVGPR(MRI, Reg); in spillVGPRtoAGPR() local1470 if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) { in spillVGPRtoAGPR()1480 unsigned Opc = (IsStore ^ IsVGPR) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64 in spillVGPRtoAGPR()