Searched refs:IsRet (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVCallingConv.h | 24 bool IsFixed, bool IsRet, Type *OrigTy);
28 CCState &State, bool IsFixed, bool IsRet, Type *OrigTy);
32 CCState &State, bool IsFixed, bool IsRet, Type *OrigTy);
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| H A D | RISCVCallingConv.cpp | 327 CCState &State, bool IsFixed, bool IsRet, Type *OrigTy) { in CC_RISCV() argument
361 if (!LocVT.isVector() && IsRet && ValNo > 1) in CC_RISCV()
564 if (IsRet) in CC_RISCV()
624 bool IsFixed, bool IsRet, Type *OrigTy) { in CC_RISCV_FastCC() argument
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| H A D | RISCVISelLowering.h | 479 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
483 bool IsRet, CallLoweringInfo *CLI,
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| H A D | RISCVISelLowering.cpp | 22026 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet, in analyzeInputArgs() argument
22035 if (IsRet) in analyzeInputArgs()
22041 /*IsFixed=*/true, IsRet, ArgTy)) { in analyzeInputArgs()
22051 const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet, in analyzeOutputArgs() argument
22059 IsRet, OrigTy)) { in analyzeOutputArgs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 37 bool IsRet; member
40 RISCVOutgoingValueAssigner(RISCVCCAssignFn *RISCVAssignFn_, bool IsRet) in RISCVOutgoingValueAssigner()
42 RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet) {} in RISCVOutgoingValueAssigner()
49 IsRet, Info.Ty)) in assignArg()
183 bool IsRet; member
186 RISCVIncomingValueAssigner(RISCVCCAssignFn *RISCVAssignFn_, bool IsRet) in RISCVIncomingValueAssigner()
188 RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet) {} in RISCVIncomingValueAssigner()
200 /*IsFixed=*/true, IsRet, Info.Ty)) in assignArg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.h | 333 bool IsFixed, bool IsRet, Type *OrigTy);
336 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
340 bool IsRet, CallLoweringInfo *CLI,
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| H A D | LoongArchISelLowering.cpp | 6697 CCState &State, bool IsFixed, bool IsRet, in CC_LoongArch() argument
6706 if (IsRet && ValNo > 1) in CC_LoongArch()
6871 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet, in analyzeInputArgs() argument
6877 if (IsRet) in analyzeInputArgs()
6884 CCInfo, /*IsFixed=*/true, IsRet, ArgTy)) { in analyzeInputArgs()
6894 const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet, in analyzeOutputArgs() argument
6902 CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) { in analyzeOutputArgs()
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