Searched refs:IsPostRA (Results 1 – 4 of 4) sorted by relevance
1577 bool IsPostRA = Phase == AMDGPU::SchedulingPhase::PostRA; in applyIGLPStrategy() local1578 assert(IsPostRA || MFMAChainSeeds.size() == MFMAChains); in applyIGLPStrategy()1580 bool UsesFMA = IsSmallKernelType || !IsPostRA; in applyIGLPStrategy()1581 bool UsesDSRead = IsLargeKernelType && !IsPostRA && FirstPipeDSR; in applyIGLPStrategy()1582 bool UsesCvt = HasCvt && (IsSmallKernelType || !IsPostRA); in applyIGLPStrategy()1590 if (!IsPostRA && MFMAChains) { in applyIGLPStrategy()1603 if (!IsPostRA && MFMAChains) { in applyIGLPStrategy()1625 if (!IsPostRA && MFMAChains) in applyIGLPStrategy()1657 if (!IsPostRA && MFMAChains) { in applyIGLPStrategy()1671 if (!IsPostRA && MFMAChains) in applyIGLPStrategy()[all …]
36 bool IsPostRA; member in __anon1ecff9b30111::SIShrinkInstructions421 if (!IsPostRA) in shrinkMadFma()849 IsPostRA = MF.getProperties().hasNoVRegs(); in run()868 if (Src.isImm() && IsPostRA) { in run()957 if (IsPostRA && TII->isMIMG(MI.getOpcode()) && in run()1075 !IsPostRA) in run()
3332 void GenericSchedulerBase::setPolicy(CandPolicy &Policy, bool IsPostRA, in setPolicy() argument3358 (IsPostRA || shouldReduceLatency(Policy, CurrZone, !RemLatencyComputed, in setPolicy()3537 bool IsPostRA = false) { in tracePick() argument3540 << (IsPostRA ? "post-RA" : "pre-RA") << "]\n"); in tracePick()3542 if (IsPostRA) { in tracePick()3665 bool IsPostRA = false) { in tracePick() argument3666 tracePick(Cand.Reason, Cand.AtTop, IsPostRA); in tracePick()
1201 LLVM_ABI void setPolicy(CandPolicy &Policy, bool IsPostRA,