Searched refs:IsFSHR (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 1541 bool IsFSHR = Opcode == ISD::FSHR; in PromoteIntRes_FunnelShift() local
1560 Res = DAG.getNode(IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, Res, Amt); in PromoteIntRes_FunnelShift()
1561 if (!IsFSHR) in PromoteIntRes_FunnelShift()
1572 if (IsFSHR) in PromoteIntRes_FunnelShift()
1593 bool IsFSHR = Opcode == ISD::VP_FSHR; in PromoteIntRes_VPFunnelShift() local
1612 Res = DAG.getNode(IsFSHR ? ISD::VP_SRL : ISD::VP_SHL, DL, VT, Res, Amt, in PromoteIntRes_VPFunnelShift()
1614 if (!IsFSHR) in PromoteIntRes_VPFunnelShift()
1625 if (IsFSHR) in PromoteIntRes_VPFunnelShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 29959 bool IsFSHR = Op.getOpcode() == ISD::FSHR; in LowerFunnelShift() local
29967 if (IsFSHR) in LowerFunnelShift()
29973 return getAVX512Node(IsFSHR ? X86ISD::VSHRD : X86ISD::VSHLD, DL, VT, in LowerFunnelShift()
29976 return getAVX512Node(IsFSHR ? X86ISD::VSHRDV : X86ISD::VSHLDV, DL, VT, in LowerFunnelShift()
29991 uint64_t ShXAmt = IsFSHR ? (EltSizeInBits - ShiftAmt) : ShiftAmt; in LowerFunnelShift()
29992 uint64_t ShYAmt = IsFSHR ? ShiftAmt : (EltSizeInBits - ShiftAmt); in LowerFunnelShift()
30033 unsigned ShiftOpc = IsFSHR ? ISD::SRL : ISD::SHL; in LowerFunnelShift()
30062 return getPack(DAG, Subtarget, DL, VT, Lo, Hi, !IsFSHR); in LowerFunnelShift()
30086 if (!IsFSHR) in LowerFunnelShift()
30093 if (((IsCst || !Subtarget.hasAVX512()) && !IsFSHR && EltSizeInBits <= 16) || in LowerFunnelShift()
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