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Searched refs:IsAdd (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DDivisionByConstantInfo.cpp81 Retval.IsAdd = false; // initialize "add" indicator in get()
111 Retval.IsAdd = true; in get()
121 Retval.IsAdd = true; in get()
135 if (Retval.IsAdd && !D[0] && AllowEvenDivisorOptimization) { in get()
140 assert(Retval.IsAdd == 0 && Retval.PreShift == 0); in get()
149 if (Retval.IsAdd) { in get()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp451 unsigned Reg, int NumBytes, bool IsAdd, in emitRegUpdate() argument
455 Opc = IsAdd ? ARC::ADD_rru6 : ARC::SUB_rru6; in emitRegUpdate()
457 Opc = IsAdd ? ARC::ADD_rrs12 : ARC::SUB_rrs12; in emitRegUpdate()
459 Opc = IsAdd ? ARC::ADD_rrlimm : ARC::SUB_rrlimm; in emitRegUpdate()
483 bool IsAdd = (Old.getOpcode() == ARC::ADJCALLSTACKUP); in eliminateCallFramePseudoInstr() local
484 emitRegUpdate(MBB, I, dl, ARC::SP, Amt, IsAdd, TII); in eliminateCallFramePseudoInstr()
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DDivisionByConstantInfo.h34 bool IsAdd; ///< add indicator member
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopFlatten.cpp204 bool IsAdd = match(U, m_c_Add(m_Specific(InnerInductionPHI), in matchLinearIVUser() local
240 if (Widened && (IsAdd || IsGEP) && in matchLinearIVUser()
252 if ((IsAdd || IsAddTrunc || IsGEP) && MatchedItCount == InnerTripCount) { in matchLinearIVUser()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DComplexDeinterleavingPass.cpp673 auto IsAdd = [](unsigned Op) { in identifyPartialMul() local
680 if (IsAdd(Real->getOpcode()) && IsAdd(Imag->getOpcode())) in identifyPartialMul()
682 else if (IsSub(Real->getOpcode()) && IsAdd(Imag->getOpcode())) in identifyPartialMul()
686 else if (IsAdd(Real->getOpcode()) && IsSub(Imag->getOpcode())) in identifyPartialMul()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp968 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; in SelectADD_SUB_I64() local
991 unsigned Opc = OpcMap[0][N->isDivergent()][IsAdd]; in SelectADD_SUB_I64()
992 unsigned CarryOpc = OpcMap[1][N->isDivergent()][IsAdd]; in SelectADD_SUB_I64()
1051 bool IsAdd = N->getOpcode() == ISD::UADDO; in SelectUADDO_USUBO() local
1057 if ((IsAdd && (UI->getOpcode() != ISD::UADDO_CARRY)) || in SelectUADDO_USUBO()
1058 (!IsAdd && (UI->getOpcode() != ISD::USUBO_CARRY))) { in SelectUADDO_USUBO()
1065 unsigned Opc = IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64; in SelectUADDO_USUBO()
H A DAMDGPUInstructionSelector.cpp519 const bool IsAdd = I.getOpcode() == AMDGPU::G_UADDO || in selectG_UADDO_USUBO_UADDE_USUBE() local
526 IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64; in selectG_UADDO_USUBO_UADDE_USUBE()
527 unsigned CarryOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64; in selectG_UADDO_USUBO_UADDE_USUBE()
542 unsigned NoCarryOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32; in selectG_UADDO_USUBO_UADDE_USUBE()
543 unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32; in selectG_UADDO_USUBO_UADDE_USUBE()
H A DSIISelLowering.cpp5337 bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO); in EmitInstrWithCustomInserter() local
5339 unsigned Opc = IsAdd ? AMDGPU::S_ADD_U64 : AMDGPU::S_SUB_U64; in EmitInstrWithCustomInserter()
5362 unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32; in EmitInstrWithCustomInserter()
5363 unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32; in EmitInstrWithCustomInserter()
5386 bool IsAdd = (MI.getOpcode() == AMDGPU::V_ADD_U64_PSEUDO); in EmitInstrWithCustomInserter() local
5392 if (IsAdd && ST.hasLshlAddU64Inst()) { in EmitInstrWithCustomInserter()
5434 IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64; in EmitInstrWithCustomInserter()
5441 unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64; in EmitInstrWithCustomInserter()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp8861 const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO; in lowerSADDO_SSUBO() local
8868 if (IsAdd) in lowerSADDO_SSUBO()
8886 IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero); in lowerSADDO_SSUBO()
8901 bool IsAdd; in lowerAddSubSatToMinMax() local
8908 IsAdd = true; in lowerAddSubSatToMinMax()
8913 IsAdd = true; in lowerAddSubSatToMinMax()
8918 IsAdd = false; in lowerAddSubSatToMinMax()
8923 IsAdd = false; in lowerAddSubSatToMinMax()
8945 if (IsAdd) { in lowerAddSubSatToMinMax()
8962 Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS; in lowerAddSubSatToMinMax()
[all …]
H A DCombinerHelper.cpp5398 assert((!magics.IsAdd || magics.PreShift == 0) && "Unexpected pre-shift"); in buildUDivorURemUsingMul()
5401 SelNPQ = magics.IsAdd; in buildUDivorURemUsingMul()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp6735 assert((!magics.IsAdd || magics.PreShift == 0) && in BuildUDIV()
6740 magics.IsAdd ? APInt::getOneBitSet(EltBits, EltBits - 1) in BuildUDIV()
6743 UseNPQ |= magics.IsAdd; in BuildUDIV()
11378 bool IsAdd = Node->getOpcode() == ISD::UADDO; in expandUADDSUBO() local
11381 unsigned OpcCarry = IsAdd ? ISD::UADDO_CARRY : ISD::USUBO_CARRY; in expandUADDSUBO()
11391 Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl, in expandUADDSUBO()
11398 if (IsAdd && isOneConstant(RHS)) { in expandUADDSUBO()
11407 } else if (IsAdd && isAllOnesConstant(RHS)) { in expandUADDSUBO()
11413 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT; in expandUADDSUBO()
11424 bool IsAdd = Node->getOpcode() == ISD::SADDO; in expandSADDSUBO() local
[all …]
H A DDAGCombiner.cpp2620 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubBoolOfMaskedVal() local
2621 SDValue C = IsAdd ? N->getOperand(1) : N->getOperand(0); in foldAddSubBoolOfMaskedVal()
2622 SDValue Z = IsAdd ? N->getOperand(0) : N->getOperand(1); in foldAddSubBoolOfMaskedVal()
2642 SDValue C1 = IsAdd ? DAG.getConstant(CN->getAPIntValue() + 1, DL, VT) in foldAddSubBoolOfMaskedVal()
2644 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit); in foldAddSubBoolOfMaskedVal()
2755 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubOfSignBit() local
2756 SDValue ConstantOp = IsAdd ? N->getOperand(1) : N->getOperand(0); in foldAddSubOfSignBit()
2757 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1); in foldAddSubOfSignBit()
2778 IsAdd ? ISD::ADD : ISD::SUB, DL, VT, in foldAddSubOfSignBit()
2780 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT, in foldAddSubOfSignBit()
[all …]
H A DLegalizeDAG.cpp4075 bool IsAdd = Node->getOpcode() == ISD::UADDO_CARRY; in ExpandNode() local
4078 unsigned Op = IsAdd ? ISD::ADD : ISD::SUB; in ExpandNode()
4085 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT; in ExpandNode()
4100 IsAdd ? DAG.getSetCC(dl, SetCCType, Sum2, Zero, ISD::SETEQ) in ExpandNode()
H A DLegalizeIntegerTypes.cpp4713 bool IsAdd = Node->getOpcode() == ISD::SADDO; in ExpandIntRes_SADDSUBO() local
4714 unsigned CarryOp = IsAdd ? ISD::SADDO_CARRY : ISD::SSUBO_CARRY; in ExpandIntRes_SADDSUBO()
4726 Lo = DAG.getNode(IsAdd ? ISD::UADDO : ISD::USUBO, dl, VTList, {LHSL, RHSL}); in ExpandIntRes_SADDSUBO()
4763 if (IsAdd) in ExpandIntRes_SADDSUBO()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1991 bool IsAdd = (Opc == Intrinsic::sadd_sat || Opc == Intrinsic::ssub_sat); in getIntrinsicInstrCost() local
2004 return getArithmeticInstrCost(IsAdd ? Instruction::Add : Instruction::Sub, in getIntrinsicInstrCost()
/freebsd/contrib/llvm-project/clang/lib/AST/ByteCode/
H A DInterpBuiltin.cpp1416 bool IsAdd = BuiltinOp == clang::X86::BI__builtin_ia32_addcarryx_u32 || in interp__builtin_ia32_addcarry_subborrow() local
1422 IsAdd ? (LHS.zext(BitWidth + 1) + (RHS.zext(BitWidth + 1) + CarryInBit)) in interp__builtin_ia32_addcarry_subborrow()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp12477 bool IsAdd = Opc == ISD::UADDO; in LowerADDSUBO() local
12478 Opc = IsAdd ? PPCISD::ADDC : PPCISD::SUBC; in LowerADDSUBO()
12483 if (!IsAdd) in LowerADDSUBO()
12497 bool IsAdd = Opc == ISD::UADDO_CARRY; in LowerADDSUBO_CARRY() local
12498 Opc = IsAdd ? PPCISD::ADDE : PPCISD::SUBE; in LowerADDSUBO_CARRY()
12499 if (!IsAdd) in LowerADDSUBO_CARRY()
12507 if (!IsAdd) in LowerADDSUBO_CARRY()
19233 bool IsAdd = ((N.getOpcode() == ISD::ADD) || (N.getOpcode() == ISD::OR)); in setAlignFlagsForFI() local
19234 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(IsAdd ? N.getOperand(0) : N); in setAlignFlagsForFI()
19248 if (!IsAdd) { in setAlignFlagsForFI()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSelect.cpp2166 auto IsSignedSaturateLimit = [&](Value *Limit, bool IsAdd) { in foldOverflowingAddSubSelect() argument
2187 if (IsAdd) { in foldOverflowingAddSubSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp14396 bool IsAdd = N->getOpcode() == ISD::UADDO; in ReplaceNodeResults() local
14401 DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, DL, MVT::i64, LHS, RHS); in ReplaceNodeResults()
14406 if (IsAdd && isOneConstant(RHS)) { in ReplaceNodeResults()
14414 } else if (IsAdd && isAllOnesConstant(RHS)) { in ReplaceNodeResults()
14424 IsAdd ? ISD::SETULT : ISD::SETUGT); in ReplaceNodeResults()
15954 bool IsAdd = (E & 3) == 1; in expandMulToNAFSequence() local
15955 E -= IsAdd ? 1 : -1; in expandMulToNAFSequence()
15958 ISD::NodeType AddSubOp = IsAdd ? ISD::ADD : ISD::SUB; in expandMulToNAFSequence()
18154 bool IsAdd = N0.getOpcode() == ISD::ADD; in performSRACombine() local
18155 if ((IsAdd || N0.getOpcode() == ISD::SUB)) { in performSRACombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1106 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; in performMADD_MSUBCombine() local
1107 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd) in performMADD_MSUBCombine()
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaOpenMP.cpp8324 bool IsAdd = BO->getOpcode() == BO_Add; in checkAndSetIncRHS() local
8326 return setStep(BO->getRHS(), !IsAdd); in checkAndSetIncRHS()
8327 if (IsAdd && getInitLCDecl(BO->getRHS()) == LCDecl) in checkAndSetIncRHS()
8331 bool IsAdd = CE->getOperator() == OO_Plus; in checkAndSetIncRHS() local
8332 if ((IsAdd || CE->getOperator() == OO_Minus) && CE->getNumArgs() == 2) { in checkAndSetIncRHS()
8334 return setStep(CE->getArg(1), !IsAdd); in checkAndSetIncRHS()
8335 if (IsAdd && getInitLCDecl(CE->getArg(1)) == LCDecl) in checkAndSetIncRHS()
/freebsd/contrib/llvm-project/clang/lib/AST/
H A DExprConstant.cpp13885 bool IsAdd = BuiltinOp == clang::X86::BI__builtin_ia32_addcarryx_u32 || in VisitBuiltinCallExpr() local
13891 IsAdd in VisitBuiltinCallExpr()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp20813 static SDValue foldOverflowCheck(SDNode *Op, SelectionDAG &DAG, bool IsAdd) { in foldOverflowCheck() argument
20818 if (IsAdd) { in foldOverflowCheck()
20826 SDValue CsetOp = CmpOp->getOperand(IsAdd ? 0 : 1); in foldOverflowCheck()
20828 if (CC != (IsAdd ? AArch64CC::HS : AArch64CC::LO)) in foldOverflowCheck()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp33047 bool IsAdd = Opc == ISD::UADDO_CARRY || Opc == ISD::SADDO_CARRY; in LowerADDSUBO_CARRY() local
33048 SDValue Sum = DAG.getNode(IsAdd ? X86ISD::ADC : X86ISD::SBB, DL, VTs, in LowerADDSUBO_CARRY()
53871 bool IsAdd = (Opcode == ISD::FADD) || (Opcode == ISD::ADD); in combineToHorizontalAddSub() local
53888 auto HorizOpcode = IsAdd ? X86ISD::FHADD : X86ISD::FHSUB; in combineToHorizontalAddSub()
53889 if (isHorizontalBinOp(HorizOpcode, LHS, RHS, DAG, Subtarget, IsAdd, in combineToHorizontalAddSub()
53905 auto HorizOpcode = IsAdd ? X86ISD::HADD : X86ISD::HSUB; in combineToHorizontalAddSub()
53906 if (isHorizontalBinOp(HorizOpcode, LHS, RHS, DAG, Subtarget, IsAdd, in combineToHorizontalAddSub()