Searched refs:IsAGPR (Results 1 – 7 of 7) sorted by relevance
193 bool IsAGPR = false; in analyzeResourceUsage() local282 IsAGPR = true; in analyzeResourceUsage()292 IsAGPR = true; in analyzeResourceUsage()302 IsAGPR = true; in analyzeResourceUsage()312 IsAGPR = true; in analyzeResourceUsage()322 IsAGPR = true; in analyzeResourceUsage()332 IsAGPR = true; in analyzeResourceUsage()342 IsAGPR = true; in analyzeResourceUsage()352 IsAGPR = true; in analyzeResourceUsage()362 IsAGPR = true; in analyzeResourceUsage()[all …]
119 bool IsAGPR; member810 IsAGPR = LSO.TRI->hasAGPRs(LSO.getDataRegClass(*MI)); in setMI()2305 AddrList.front().IsAGPR == CI.IsAGPR && in addInstToMergeableList()2361 if (CI.InstClass == DS_WRITE && CI.IsAGPR) { in collectMergeableInsts()
324 bool IsAGPR = TRI->isAGPRClass(DstRC); in foldVGPRCopyIntoRegSequence() local339 if (IsAGPR) { in foldVGPRCopyIntoRegSequence()
1592 const bool IsAGPR = !ST.hasGFX90AInsts() && isAGPRClass(RC); in buildSpillLoadStore() local1599 : (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) in buildSpillLoadStore()1858 if (IsAGPR) { in buildSpillLoadStore()1897 MIB.addReg(TmpOffsetVGPR, getKillRegState(IsLastSubReg && !IsAGPR)); in buildSpillLoadStore()1925 if (!IsAGPR && NeedSuperRegDef) in buildSpillLoadStore()1928 if (!IsStore && IsAGPR && TmpIntermediateVGPR != AMDGPU::NoRegister) { in buildSpillLoadStore()
2201 bool IsAGPR = SIRegisterInfo::isAGPRClass(RI.getPhysRegBaseClass(Dst)); in expandPostRAPseudo() local2203 get(IsAGPR ? AMDGPU::V_ACCVGPR_WRITE_B32_e64 : AMDGPU::V_MOV_B32_e32)); in expandPostRAPseudo()5980 bool IsAGPR = RI.isAGPR(MRI, MO.getReg()); in isLegalRegOperand() local5981 if (IsAGPR && !ST.hasMAIInsts()) in isLegalRegOperand()5983 if (IsAGPR && (!ST.hasGFX90AInsts() || !MRI.reservedRegsFrozen()) && in isLegalRegOperand()5992 RI.isAGPR(MRI, MI.getOperand(DataIdx).getReg()) != IsAGPR) in isLegalRegOperand()5996 RI.isAGPR(MRI, MI.getOperand(VDstIdx).getReg()) != IsAGPR) in isLegalRegOperand()6001 RI.isAGPR(MRI, MI.getOperand(Data1Idx).getReg()) != IsAGPR) in isLegalRegOperand()10405 bool IsAGPR = RI.isAGPR(MRI, DataReg); in enforceOperandRCAlignment() local10407 IsAGPR ? &AMDGPU::AGPR_32RegClass : &AMDGPU::VGPR_32RegClass); in enforceOperandRCAlignment()[all …]
557 bool IsAGPR = Enc & AMDGPU::HWEncoding::IS_AGPR; in getAVOperandEncoding() local559 Op = Idx | (IsVGPROrAGPR << 8) | (IsAGPR << 9); in getAVOperandEncoding()
1778 bool IsAGPR = Val & 512; in decodeSrcOp() local1782 return createRegOperand(IsAGPR ? getAgprClassId(Width) in decodeSrcOp()