Searched refs:IsAGPR (Results 1 – 7 of 7) sorted by relevance
269 bool IsAGPR = false; in analyzeResourceUsage() local358 IsAGPR = true; in analyzeResourceUsage()368 IsAGPR = true; in analyzeResourceUsage()378 IsAGPR = true; in analyzeResourceUsage()388 IsAGPR = true; in analyzeResourceUsage()398 IsAGPR = true; in analyzeResourceUsage()408 IsAGPR = true; in analyzeResourceUsage()418 IsAGPR = true; in analyzeResourceUsage()428 IsAGPR = true; in analyzeResourceUsage()438 IsAGPR = true; in analyzeResourceUsage()[all …]
118 bool IsAGPR; member774 IsAGPR = LSO.TRI->hasAGPRs(LSO.getDataRegClass(*MI)); in setMI()2235 AddrList.front().IsAGPR == CI.IsAGPR && in addInstToMergeableList()2291 if (CI.InstClass == DS_WRITE && CI.IsAGPR) { in collectMergeableInsts()
1351 const bool IsAGPR = !ST.hasGFX90AInsts() && isAGPRClass(RC); in buildSpillLoadStore() local1356 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u; in buildSpillLoadStore()1613 if (IsAGPR) { in buildSpillLoadStore()1650 MIB.addReg(TmpOffsetVGPR, getKillRegState(IsLastSubReg && !IsAGPR)); in buildSpillLoadStore()1678 if (!IsAGPR && NeedSuperRegDef) in buildSpillLoadStore()1681 if (!IsStore && IsAGPR && TmpIntermediateVGPR != AMDGPU::NoRegister) { in buildSpillLoadStore()
310 bool IsAGPR = TRI->isAGPRClass(DstRC); in foldVGPRCopyIntoRegSequence() local325 if (IsAGPR) { in foldVGPRCopyIntoRegSequence()
5782 bool IsAGPR = RI.isAGPR(MRI, MO->getReg()); in isOperandLegal() local5783 if (IsAGPR && !ST.hasMAIInsts()) in isOperandLegal()5786 if (IsAGPR && in isOperandLegal()5796 RI.isAGPR(MRI, MI.getOperand(DataIdx).getReg()) != IsAGPR) in isOperandLegal()5800 RI.isAGPR(MRI, MI.getOperand(VDstIdx).getReg()) != IsAGPR) in isOperandLegal()5806 RI.isAGPR(MRI, MI.getOperand(Data1Idx).getReg()) != IsAGPR) in isOperandLegal()9931 bool IsAGPR = RI.isAGPR(MRI, DataReg); in enforceOperandRCAlignment() local9933 IsAGPR ? &AMDGPU::AGPR_32RegClass : &AMDGPU::VGPR_32RegClass); in enforceOperandRCAlignment()9936 MRI.createVirtualRegister(IsAGPR ? &AMDGPU::AReg_64_Align2RegClass in enforceOperandRCAlignment()
541 bool IsAGPR = false; in getAVOperandEncoding() local556 IsAGPR = true; in getAVOperandEncoding()558 Op = Idx | (IsVGPROrAGPR << 8) | (IsAGPR << 9); in getAVOperandEncoding()
1528 bool IsAGPR = Val & 512; in decodeSrcOp() local1532 return createRegOperand(IsAGPR ? getAgprClassId(Width) in decodeSrcOp()