| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 6349 bool IsA16, bool IsG16) { in packImage16bitOpsToDwords() argument
6363 (I >= Intr->CoordStart && !IsA16)) { in packImage16bitOpsToDwords()
6364 if ((I < Intr->GradientStart) && IsA16 && in packImage16bitOpsToDwords()
6373 assert((!IsA16 || Intr->NumBiasArgs == 0 || I != Intr->BiasIndex) && in packImage16bitOpsToDwords()
6486 const bool IsA16 = AddrTy == S16; in legalizeImageIntrinsic() local
6549 if (BaseOpcode->Gradients && !ST.hasG16() && (IsA16 != IsG16)) { in legalizeImageIntrinsic()
6555 if (IsA16 && !ST.hasA16()) { in legalizeImageIntrinsic()
6563 if (IsA16 || IsG16) { in legalizeImageIntrinsic()
6568 packImage16bitOpsToDwords(B, MI, PackedRegs, ArgOffset, Intr, IsA16, IsG16); in legalizeImageIntrinsic()
6639 if (IsA16) in legalizeImageIntrinsic()
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| H A D | MIMGInstructions.td | 1515 class MIMG_IntersectRay_Helper<bit Is64, bit IsA16, bit isDual, bit isBVH8> {
1516 int num_addrs = !if(isBVH8, 11, !if(Is64, !if(IsA16, 9, 12), !if(IsA16, 8, 11)));
1520 int GFX11PlusNSAAddrs = !if(IsA16, 4, 5);
1525 IsA16 : [node_ptr_type, VGPR_32, VReg_96, VReg_96],
1577 multiclass MIMG_IntersectRay<mimgopc op, string opcode, bit Is64, bit IsA16,
1579 defvar info = MIMG_IntersectRay_Helper<Is64, IsA16, isDual, isBVH8>;
1582 let A16 = IsA16;
1590 a16 = IsA16,
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| H A D | SIISelLowering.cpp | 8477 bool IsA16 = false; in lowerImage() local
8570 IsA16 = VAddrScalarVT == MVT::f16 || VAddrScalarVT == MVT::i16; in lowerImage()
8574 if (IsA16 && (Op.getOperand(ArgOffset + I).getValueType() == MVT::f16)) { in lowerImage()
8583 assert((!IsA16 || Intr->NumBiasArgs == 0 || I != Intr->BiasIndex) && in lowerImage()
8589 if (BaseOpcode->Gradients && !ST->hasG16() && (IsA16 != IsG16)) { in lowerImage()
8598 if (IsA16) { in lowerImage()
8632 if (IsA16) { in lowerImage()
8763 Ops.push_back(IsA16 && // r128, a16 for gfx9 in lowerImage()
8768 Ops.push_back(IsA16 ? True : False); in lowerImage()
9820 const bool IsA16 = RayDir.getValueType().getVectorElementType() == MVT::f16; in LowerINTRINSIC_W_CHAIN() local
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| H A D | AMDGPUInstructionSelector.cpp | 2065 const bool IsA16 = (Flags & 1) != 0; in selectImageIntrinsic() local
2069 if (IsA16 && !STI.hasG16() && !IsG16) in selectImageIntrinsic()
2244 MIB.addImm(IsA16 && // a16 or r128 in selectImageIntrinsic()
2247 MIB.addImm(IsA16 ? -1 : 0); in selectImageIntrinsic()
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| H A D | SIInstrInfo.cpp | 5347 bool IsA16 = false; in verifyInstruction() local
5350 IsA16 = R128A16->getImm() != 0; in verifyInstruction()
5353 IsA16 = A16->getImm() != 0; in verifyInstruction()
5359 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, ST.hasG16()); in verifyInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 322 const MIMGDimInfo *Dim, bool IsA16, in getAddrSizeMIMGOp() argument
327 if (IsA16) in getAddrSizeMIMGOp()
338 if ((IsA16 && !IsG16Supported) || BaseOpcode->G16) in getAddrSizeMIMGOp()
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| H A D | AMDGPUBaseInfo.h | 514 const MIMGDimInfo *Dim, bool IsA16,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 1216 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); in convertMIMGInst() local
1219 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); in convertMIMGInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 4190 bool IsA16 = (A16Idx != -1 && Inst.getOperand(A16Idx).getImm()); in validateMIMGAddrSize() local
4192 if (IsA16 == BaseOpcode->A16) in validateMIMGAddrSize()
4206 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, DimInfo, IsA16, hasG16()); in validateMIMGAddrSize()
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