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Searched refs:Intf (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocEvictionAdvisor.cpp268 for (const LiveInterval *Intf : reverse(Interferences)) { in canEvictInterferenceBasedOnCost() local
269 assert(Intf->reg().isVirtual() && in canEvictInterferenceBasedOnCost()
275 if (FixedRegisters.count(Intf->reg())) in canEvictInterferenceBasedOnCost()
279 if (RA.getExtraInfo().getStage(*Intf) == RS_Done) in canEvictInterferenceBasedOnCost()
289 (Intf->isSpillable() || in canEvictInterferenceBasedOnCost()
292 MRI->getRegClass(Intf->reg()))); in canEvictInterferenceBasedOnCost()
294 unsigned IntfCascade = RA.getExtraInfo().getCascade(Intf->reg()); in canEvictInterferenceBasedOnCost()
306 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg()); in canEvictInterferenceBasedOnCost()
309 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight()); in canEvictInterferenceBasedOnCost()
316 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint)) in canEvictInterferenceBasedOnCost()
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H A DRegAllocGreedy.cpp639 for (const LiveInterval *Intf : Intfs) { in evictInterference() local
641 if (!VRM->hasPhys(Intf->reg())) in evictInterference()
644 Matrix->unassign(*Intf); in evictInterference()
645 assert((ExtraInfo->getCascade(Intf->reg()) < Cascade || in evictInterference()
646 VirtReg.isSpillable() < Intf->isSpillable()) && in evictInterference()
648 ExtraInfo->setCascade(Intf->reg(), Cascade); in evictInterference()
650 NewVRegs.push_back(Intf->reg()); in evictInterference()
735 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf, in addSplitConstraints() argument
747 Intf.moveToBlock(BC.Number); in addSplitConstraints()
755 if (!Intf.hasInterference()) in addSplitConstraints()
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H A DRegAllocBasic.cpp219 for (const auto *Intf : reverse(Q.interferingVRegs())) { in spillInterferences() local
220 if (!Intf->isSpillable() || Intf->weight() > VirtReg.weight()) in spillInterferences()
222 Intfs.push_back(Intf); in spillInterferences()
H A DMLRegAllocEvictAdvisor.cpp695 for (const LiveInterval *Intf : reverse(IFIntervals)) { in loadInterferenceFeatures() local
696 assert(Intf->reg().isVirtual() && in loadInterferenceFeatures()
704 if (FixedRegisters.count(Intf->reg())) in loadInterferenceFeatures()
706 if (RA.getExtraInfo().getStage(*Intf) == RS_Done) in loadInterferenceFeatures()
710 (Intf->isSpillable() || in loadInterferenceFeatures()
713 MRI->getRegClass(Intf->reg()))); in loadInterferenceFeatures()
715 unsigned IntfCascade = RA.getExtraInfo().getCascade(Intf->reg()); in loadInterferenceFeatures()
722 if (getEvictionCount(Intf->reg()) > MaxEvictionCount && !Urgent) in loadInterferenceFeatures()
732 LocalIntfs += (IsLocal && LIS->intervalIsInOneMBB(*Intf) && in loadInterferenceFeatures()
733 (!EnableLocalReassign || !canReassign(*Intf, PhysReg))); in loadInterferenceFeatures()
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H A DMLRegallocEvictAdvisor.cpp
H A DRegAllocGreedy.h236 InterferenceCache::Cursor Intf; member
245 Intf.setPhysReg(Cache, Reg); in reset()