| /freebsd/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | CoalescingBitVector.h | 57 : Alloc(&Alloc), Intervals(Alloc) {} in CoalescingBitVector()
63 : Alloc(Other.Alloc), Intervals(*Other.Alloc) { in CoalescingBitVector()
79 void clear() { Intervals.clear(); } in clear()
82 bool empty() const { return Intervals.empty(); } in empty()
87 for (auto It = Intervals.begin(), End = Intervals.end(); It != End; ++It) in count()
108 for (auto It = Other.Intervals.begin(), End = Other.Intervals.end(); in set()
121 const auto It = Intervals.find(Index); in test()
122 if (It == Intervals.end()) in test()
136 auto It = Intervals.find(Index); in reset()
137 if (It == Intervals.end()) in reset()
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| H A D | IntervalTree.h | 287 IntervalVector Intervals; // Storage for each interval and all of the fields variable
602 Intervals.clear(); in clear()
611 Intervals.emplace_back(Left, Right, Value); in insert()
651 for (const DataType &Data : Intervals) { in create()
662 IntervalsLeft.resize(Intervals.size()); in create()
663 IntervalsRight.resize(Intervals.size()); in create()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNNSAReassign.cpp | 85 bool tryAssignRegisters(SmallVectorImpl<LiveInterval *> &Intervals,
90 bool scavengeRegs(SmallVectorImpl<LiveInterval *> &Intervals) const;
109 GCNNSAReassign::tryAssignRegisters(SmallVectorImpl<LiveInterval *> &Intervals, in tryAssignRegisters() argument
111 unsigned NumRegs = Intervals.size(); in tryAssignRegisters()
114 if (VRM->hasPhys(Intervals[N]->reg())) in tryAssignRegisters()
115 LRM->unassign(*Intervals[N]); in tryAssignRegisters()
118 if (LRM->checkInterference(*Intervals[N], MCRegister::from(StartReg + N))) in tryAssignRegisters()
122 LRM->assign(*Intervals[N], MCRegister::from(StartReg + N)); in tryAssignRegisters()
143 GCNNSAReassign::scavengeRegs(SmallVectorImpl<LiveInterval *> &Intervals) const { in scavengeRegs()
144 unsigned NumRegs = Intervals.size(); in scavengeRegs()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RenameIndependentSubregs.cpp | 91 const SmallVectorImpl<LiveInterval*> &Intervals) const;
96 const SmallVectorImpl<LiveInterval*> &Intervals) const;
101 const SmallVectorImpl<LiveInterval*> &Intervals) const;
135 SmallVector<LiveInterval*, 4> Intervals; in INITIALIZE_PASS_DEPENDENCY() local
136 Intervals.push_back(&LI); in INITIALIZE_PASS_DEPENDENCY()
144 Intervals.push_back(&NewLI); in INITIALIZE_PASS_DEPENDENCY()
149 rewriteOperands(Classes, SubRangeInfos, Intervals); in INITIALIZE_PASS_DEPENDENCY()
150 distribute(Classes, SubRangeInfos, Intervals); in INITIALIZE_PASS_DEPENDENCY()
151 computeMainRangesFixFlags(Classes, SubRangeInfos, Intervals); in INITIALIZE_PASS_DEPENDENCY()
213 const SmallVectorImpl<LiveInterval*> &Intervals) const { in rewriteOperands()
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| H A D | StackColoring.cpp | 412 SmallVector<std::unique_ptr<LiveInterval>, 16> Intervals; member in __anon570007070111::StackColoring
558 for (unsigned I = 0, E = Intervals.size(); I != E; ++I) { in dumpIntervals()
560 Intervals[I]->dump(); in dumpIntervals()
868 VNInfo *VNI = Intervals[Slot]->getValNumInfo(0); in calculateLiveIntervals()
869 Intervals[Slot]->addSegment( in calculateLiveIntervals()
884 VNInfo *VNI = Intervals[i]->getValNumInfo(0); in calculateLiveIntervals()
885 Intervals[i]->addSegment(LiveInterval::Segment(Starts[i], EndIdx, VNI)); in calculateLiveIntervals()
1035 const LiveInterval *Interval = &*Intervals[FromSlot]; in remapInstructions()
1149 if (Intervals[Slot]->empty()) in removeInvalidSlotRanges()
1154 LiveInterval *Interval = &*Intervals[Slot]; in removeInvalidSlotRanges()
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| H A D | StackSlotColoring.cpp | 257 SmallVector<Pair *, 16> Intervals; in InitializeSlots() local
259 Intervals.reserve(LS->getNumIntervals()); in InitializeSlots()
261 Intervals.push_back(&I); in InitializeSlots()
262 llvm::sort(Intervals, in InitializeSlots()
267 for (auto *I : Intervals) { in InitializeSlots()
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| H A D | MLRegallocEvictAdvisor.cpp | |
| H A D | MLRegAllocEvictAdvisor.cpp | 328 void extractFeatures(const SmallVectorImpl<const LiveInterval *> &Intervals,
847 const SmallVectorImpl<const LiveInterval *> &Intervals, in extractFeatures() argument
868 Intervals.empty() ? 0 : std::numeric_limits<int64_t>::max(); in extractFeatures()
870 for (const auto *L : Intervals) { in extractFeatures()
906 if (!Intervals.empty()) { in extractFeatures()
924 SET(is_free, int64_t, Intervals.empty()); in extractFeatures()
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| /freebsd/contrib/llvm-project/compiler-rt/lib/fuzzer/ |
| H A D | FuzzerDataFlowTrace.cpp | 194 std::vector<double> Intervals(NumFunctions + 1); in Init() local
195 std::iota(Intervals.begin(), Intervals.end(), 0); in Init()
197 Intervals.begin(), Intervals.end(), Weights.begin()); in Init()
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| H A D | FuzzerCorpus.h | 508 Intervals.resize(N + 1); in UpdateCorpusDistribution()
510 std::iota(Intervals.begin(), Intervals.end(), 0); in UpdateCorpusDistribution()
566 Intervals.begin(), Intervals.end(), Weights.begin()); in UpdateCorpusDistribution()
570 std::vector<double> Intervals;
569 std::vector<double> Intervals; global() variable
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineScheduler.h | 810 explicit ResourceSegments(const std::list<IntervalTy> &Intervals) in ResourceSegments() argument
811 : _Intervals(Intervals) { in ResourceSegments()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 28561 IMap Intervals(A); in parallelizeChainedStores() local
28586 Intervals.insert(0, (St->getMemoryVT().getSizeInBits() + 7) / 8, in parallelizeChainedStores()
28609 auto I = Intervals.find(Offset); in parallelizeChainedStores()
28611 if (I != Intervals.end() && I.start() < (Offset + Length)) in parallelizeChainedStores()
28614 if (I != Intervals.begin() && (--I).stop() <= Offset) in parallelizeChainedStores()
28616 Intervals.insert(Offset, Offset + Length, std::monostate{}); in parallelizeChainedStores()
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