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Searched refs:IntVT (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1730 EVT IntVT = VT.changeVectorElementTypeToInteger(); in ExpandVP_FNEG() local
1732 if (!TLI.isOperationLegalOrCustom(ISD::VP_XOR, IntVT)) in ExpandVP_FNEG()
1739 SDValue Cast = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0)); in ExpandVP_FNEG()
1741 APInt::getSignMask(IntVT.getScalarSizeInBits()), DL, IntVT); in ExpandVP_FNEG()
1742 SDValue Xor = DAG.getNode(ISD::VP_XOR, DL, IntVT, Cast, SignMask, Mask, EVL); in ExpandVP_FNEG()
1748 EVT IntVT = VT.changeVectorElementTypeToInteger(); in ExpandVP_FABS() local
1750 if (!TLI.isOperationLegalOrCustom(ISD::VP_AND, IntVT)) in ExpandVP_FABS()
1757 SDValue Cast = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0)); in ExpandVP_FABS()
1759 APInt::getSignedMaxValue(IntVT.getScalarSizeInBits()), DL, IntVT); in ExpandVP_FABS()
1761 DAG.getNode(ISD::VP_AND, DL, IntVT, Cast, ClearSignMask, Mask, EVL); in ExpandVP_FABS()
[all …]
H A DFunctionLoweringInfo.cpp452 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local
454 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo()
456 IntVT = TLI->getRegisterType(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
457 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
H A DFastISel.cpp302 EVT IntVT = TLI.getPointerTy(DL); in materializeConstant() local
303 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeConstant()
311 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant()
1683 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in selectFNeg() local
1684 if (!TLI.isTypeLegal(IntVT)) in selectFNeg()
1687 Register IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg()
1693 IntVT.getSimpleVT(), ISD::XOR, IntReg, in selectFNeg()
1694 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg()
1698 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
H A DTargetLowering.cpp8410 EVT IntVT = SrcVT.changeTypeToInteger(); in expandFP_TO_SINT() local
8411 EVT IntShVT = getShiftAmountTy(IntVT, DAG.getDataLayout()); in expandFP_TO_SINT()
8413 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); in expandFP_TO_SINT()
8414 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); in expandFP_TO_SINT()
8415 SDValue Bias = DAG.getConstant(127, dl, IntVT); in expandFP_TO_SINT()
8416 SDValue SignMask = DAG.getConstant(APInt::getSignMask(SrcEltBits), dl, IntVT); in expandFP_TO_SINT()
8417 SDValue SignLowBit = DAG.getConstant(SrcEltBits - 1, dl, IntVT); in expandFP_TO_SINT()
8418 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); in expandFP_TO_SINT()
8420 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Src); in expandFP_TO_SINT()
8423 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
[all …]
H A DLegalizeDAG.cpp1706 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFCOPYSIGN() local
1707 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFCOPYSIGN()
1708 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN()
1718 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1719 DAG.getConstant(0, DL, IntVT), ISD::SETNE); in ExpandFCOPYSIGN()
1733 EVT ShiftVT = IntVT; in ExpandFCOPYSIGN()
1763 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFNEG() local
1766 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFNEG()
1768 DAG.getNode(ISD::XOR, DL, IntVT, SignAsInt.IntValue, SignMask); in ExpandFNEG()
1788 EVT IntVT = ValueAsInt.IntValue.getValueType(); in ExpandFABS() local
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H A DDAGCombiner.cpp2673 EVT IntVT = N1.getValueType(); in visitPTRADD() local
2678 assert(PtrVT == IntVT && in visitPTRADD()
2686 if (PtrVT == IntVT && isNullConstant(N0)) in visitPTRADD()
2707 SDValue Add = DAG.getNode(ISD::ADD, DL, IntVT, {Y, Z}, Flags); in visitPTRADD()
5919 EVT IntVT = N0.getValueType().getScalarType(); in isSaturatingMinMax() local
5926 if (IntVT.getSizeInBits() >= MinBitWidth) { in isSaturatingMinMax()
21054 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VTSize.getFixedValue()); in TransformFPLoadStorePair() local
21055 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || in TransformFPLoadStorePair()
21056 !TLI.isOperationLegal(ISD::STORE, IntVT) || in TransformFPLoadStorePair()
21059 !TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), IntVT, in TransformFPLoadStorePair()
[all …]
H A DLegalizeFloatTypes.cpp1267 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in findFPToIntLibcall() local
1268 IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; in findFPToIntLibcall()
1269 ++IntVT) { in findFPToIntLibcall()
1270 Promoted = (MVT::SimpleValueType)IntVT; in findFPToIntLibcall()
H A DSelectionDAG.cpp8242 EVT IntVT = VT.getScalarType(); in getMemsetValue() local
8243 if (!IntVT.isInteger()) in getMemsetValue()
8244 IntVT = EVT::getIntegerVT(*DAG.getContext(), IntVT.getSizeInBits()); in getMemsetValue()
8246 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value); in getMemsetValue()
8251 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value, in getMemsetValue()
8252 DAG.getConstant(Magic, dl, IntVT)); in getMemsetValue()
H A DLegalizeIntegerTypes.cpp4069 EVT IntVT = in ExpandIntRes_CTPOP() local
4071 SDValue Res = TLI.makeLibCall(DAG, LC, IntVT, Op, CallOptions, DL).first; in ExpandIntRes_CTPOP()
H A DSelectionDAGBuilder.cpp247 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); in getCopyFromParts() local
248 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, in getCopyFromParts()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h428 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local
429 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT()
430 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
H A DTargetLowering.h2503 virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, in shouldUseStrictFP_TO_INT() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp162 for (MVT IntVT : {MVT::i32, MVT::i64}) { in initSPUActions()
164 setOperationAction(ISD::UREM, IntVT, Expand); in initSPUActions()
165 setOperationAction(ISD::SREM, IntVT, Expand); in initSPUActions()
166 setOperationAction(ISD::SDIVREM, IntVT, Expand); in initSPUActions()
167 setOperationAction(ISD::UDIVREM, IntVT, Expand); in initSPUActions()
170 setOperationAction(ISD::SHL_PARTS, IntVT, Expand); in initSPUActions()
171 setOperationAction(ISD::SRA_PARTS, IntVT, Expand); in initSPUActions()
172 setOperationAction(ISD::SRL_PARTS, IntVT, Expand); in initSPUActions()
176 setOperationAction(ISD::MULHU, IntVT, Expand); in initSPUActions()
177 setOperationAction(ISD::MULHS, IntVT, Expand); in initSPUActions()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3304 MVT IntVT = ContainerVT.changeVectorElementTypeToInteger(); in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() local
3324 Truncated = DAG.getNode(RISCVISD::VFCVT_RM_X_F_VL, DL, IntVT, Src, Mask, in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
3329 Truncated = DAG.getNode(RISCVISD::VFCVT_RTZ_X_F_VL, DL, IntVT, Src, in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
3410 MVT IntVT = ContainerVT.changeVectorElementTypeToInteger(); in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND() local
3424 RISCVISD::STRICT_VFCVT_RM_X_F_VL, DL, DAG.getVTList(IntVT, MVT::Other), in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
3431 DAG.getVTList(IntVT, MVT::Other), Chain, Src, Mask, VL); in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
5082 MVT IntVT = ContainerVT.changeVectorElementTypeToInteger(); in lowerVECTOR_SHUFFLEAsVSlide1() local
5086 IntVT, convertToScalableVector(ContainerVT, V2, DAG, Subtarget)); in lowerVECTOR_SHUFFLEAsVSlide1()
5089 IntVT, DAG.getUNDEF(IntVT), V2, Splat, TrueMask, VL); in lowerVECTOR_SHUFFLEAsVSlide1()
5146 MVT IntVT = VT.changeVectorElementTypeToInteger(); in lowerVZIP() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp2161 EVT IntVT = MemVT.changeTypeToInteger(); in lowerKernargMemParameter() local
2173 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract); in lowerKernargMemParameter()
3061 EVT IntVT = MemVT.changeTypeToInteger(); in LowerFormalArguments() local
3076 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, DL, IntVT, Extract); in LowerFormalArguments()
6322 EVT IntVT = LoadVT.changeTypeToInteger(); in lowerIntrinsicLoad() local
6344 return getMemIntrinsicNode(Opc, DL, M->getVTList(), Ops, IntVT, in lowerIntrinsicLoad()
6467 MVT IntVT = MVT::getIntegerVT(ValSize); in lowerLaneOp() local
6534 Src0 = DAG.getAnyExtOrTrunc(IsFloat ? DAG.getBitcast(IntVT, Src0) : Src0, in lowerLaneOp()
6538 Src1 = DAG.getAnyExtOrTrunc(IsFloat ? DAG.getBitcast(IntVT, Src1) : Src1, in lowerLaneOp()
6543 Src2 = DAG.getAnyExtOrTrunc(IsFloat ? DAG.getBitcast(IntVT, Src2) : Src2, in lowerLaneOp()
[all …]
H A DAMDGPUISelLowering.cpp1968 MVT IntVT = MVT::i32; in LowerDIVREM24() local
1988 SDValue jq = DAG.getConstant(1, DL, IntVT); in LowerDIVREM24()
2039 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq); in LowerDIVREM24()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp770 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); in initActions() local
771 if (IntVT.isValid()) { in initActions()
773 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp18644 MVT IntVT = MVT::getIntegerVT(Vec.getValueType().getVectorNumElements()); in ExtractBitFromMaskVector() local
18645 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, DAG.getBitcast(IntVT, Vec)); in ExtractBitFromMaskVector()
19877 MVT IntVT = CastToInt.getSimpleValueType(); in lowerFPToIntToFP() local
19886 IntVT != MVT::i32) in lowerFPToIntToFP()
19890 unsigned IntSize = IntVT.getSizeInBits(); in lowerFPToIntToFP()
19893 MVT VecIntVT = MVT::getVectorVT(IntVT, 128 / IntSize); in lowerFPToIntToFP()
23058 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); in LowerVectorAllEqual() local
23059 if (!DAG.getTargetLoweringInfo().isTypeLegal(IntVT)) { in LowerVectorAllEqual()
23060 if (IntVT != MVT::i64) in LowerVectorAllEqual()
23062 auto SplitLHS = DAG.SplitScalar(DAG.getBitcast(IntVT, MaskBits(LHS)), DL, in LowerVectorAllEqual()
[all …]
H A DX86ISelLoweringCall.cpp1661 MVT IntVT = is64Bit() ? MVT::i64 : MVT::i32; in forwardMustTailParameters() local
1662 RegParmTypes.push_back(IntVT); in forwardMustTailParameters()
H A DX86ISelDAGToDAG.cpp1322 EVT IntVT = EVT(VecVT).changeVectorElementTypeToInteger(); in PreprocessISelDAG() local
1323 Op0 = CurDAG->getNode(ISD::BITCAST, dl, IntVT, Op0); in PreprocessISelDAG()
1324 Op1 = CurDAG->getNode(ISD::BITCAST, dl, IntVT, Op1); in PreprocessISelDAG()
1333 Res = CurDAG->getNode(Opc, dl, IntVT, Op0, Op1); in PreprocessISelDAG()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3538 EVT IntVT = C.Op0.getValueType().changeVectorElementTypeToInteger(); in emitCmp() local
3539 SDVTList VTs = DAG.getVTList(IntVT, MVT::i32); in emitCmp()
6532 MVT IntVT = MVT::getIntegerVT(VT.getScalarSizeInBits()); in lowerINSERT_VECTOR_ELT() local
6533 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements()); in lowerINSERT_VECTOR_ELT()
6536 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2); in lowerINSERT_VECTOR_ELT()
6559 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits()); in lowerEXTRACT_VECTOR_ELT() local
6560 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements()); in lowerEXTRACT_VECTOR_ELT()
6561 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, in lowerEXTRACT_VECTOR_ELT()
8691 EVT IntVT = CmpVT.changeVectorElementTypeToInteger(); in combineSETCC() local
8693 DAG.getBitcast(MVT::i128, DAG.getSExtOrTrunc(Src, DL, IntVT)); in combineSETCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4699 EVT IntVT = SrcVT.changeVectorElementTypeToInteger(); in LowerVectorFP_TO_INT_SAT() local
4700 SDValue NativeCvt = DAG.getNode(Op.getOpcode(), DL, IntVT, SrcVal, in LowerVectorFP_TO_INT_SAT()
4701 DAG.getValueType(IntVT.getScalarType())); in LowerVectorFP_TO_INT_SAT()
4703 SrcVal2 ? DAG.getNode(Op.getOpcode(), DL, IntVT, SrcVal2, in LowerVectorFP_TO_INT_SAT()
4704 DAG.getValueType(IntVT.getScalarType())) in LowerVectorFP_TO_INT_SAT()
4709 APInt::getSignedMaxValue(SatWidth).sext(SrcElementWidth), DL, IntVT); in LowerVectorFP_TO_INT_SAT()
4710 SDValue Min = DAG.getNode(ISD::SMIN, DL, IntVT, NativeCvt, MinC); in LowerVectorFP_TO_INT_SAT()
4711 SDValue Min2 = SrcVal2 ? DAG.getNode(ISD::SMIN, DL, IntVT, NativeCvt2, MinC) : SDValue(); in LowerVectorFP_TO_INT_SAT()
4713 APInt::getSignedMinValue(SatWidth).sext(SrcElementWidth), DL, IntVT); in LowerVectorFP_TO_INT_SAT()
4714 Sat = DAG.getNode(ISD::SMAX, DL, IntVT, Min, MaxC); in LowerVectorFP_TO_INT_SAT()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1025 MVT IntVT = MVT::i32; in LowerFormalArguments() local
1026 RegParmTypes.push_back(IntVT); in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp7957 EVT IntVT = Op.getValueType(); in LowerGET_DYNAMIC_AREA_OFFSET() local
7964 SDVTList VTs = DAG.getVTList(IntVT); in LowerGET_DYNAMIC_AREA_OFFSET()