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Searched refs:IntVT (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h418 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local
419 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT()
420 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
H A DTargetLowering.h2429 virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, in shouldUseStrictFP_TO_INT() argument
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp447 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local
449 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo()
451 IntVT = TLI->getRegisterType(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
452 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
H A DFastISel.cpp301 EVT IntVT = TLI.getPointerTy(DL); in materializeConstant() local
302 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeConstant()
310 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant()
1742 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in selectFNeg() local
1743 if (!TLI.isTypeLegal(IntVT)) in selectFNeg()
1746 Register IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg()
1752 IntVT.getSimpleVT(), ISD::XOR, IntReg, in selectFNeg()
1753 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg()
1757 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
H A DTargetLowering.cpp8192 EVT IntVT = SrcVT.changeTypeToInteger(); in expandFP_TO_SINT() local
8193 EVT IntShVT = getShiftAmountTy(IntVT, DAG.getDataLayout()); in expandFP_TO_SINT()
8195 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); in expandFP_TO_SINT()
8196 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); in expandFP_TO_SINT()
8197 SDValue Bias = DAG.getConstant(127, dl, IntVT); in expandFP_TO_SINT()
8198 SDValue SignMask = DAG.getConstant(APInt::getSignMask(SrcEltBits), dl, IntVT); in expandFP_TO_SINT()
8199 SDValue SignLowBit = DAG.getConstant(SrcEltBits - 1, dl, IntVT); in expandFP_TO_SINT()
8200 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); in expandFP_TO_SINT()
8202 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Src); in expandFP_TO_SINT()
8205 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
[all …]
H A DLegalizeDAG.cpp1640 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFCOPYSIGN() local
1641 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFCOPYSIGN()
1642 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN()
1651 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1652 DAG.getConstant(0, DL, IntVT), ISD::SETNE); in ExpandFCOPYSIGN()
1666 EVT ShiftVT = IntVT; in ExpandFCOPYSIGN()
1699 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFNEG() local
1702 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFNEG()
1704 DAG.getNode(ISD::XOR, DL, IntVT, SignAsInt.IntValue, SignMask); in ExpandFNEG()
1724 EVT IntVT = ValueAsInt.IntValue.getValueType(); in ExpandFABS() local
[all …]
H A DDAGCombiner.cpp5544 EVT IntVT = N0.getValueType().getScalarType(); in isSaturatingMinMax() local
5551 if (IntVT.getSizeInBits() >= MinBitWidth) { in isSaturatingMinMax()
15805 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); in ConstantFoldBITCASTofBUILD_VECTOR() local
15806 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); in ConstantFoldBITCASTofBUILD_VECTOR()
15807 SrcEltVT = IntVT; in ConstantFoldBITCASTofBUILD_VECTOR()
20036 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VTSize.getFixedValue()); in TransformFPLoadStorePair() local
20037 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || in TransformFPLoadStorePair()
20038 !TLI.isOperationLegal(ISD::STORE, IntVT) || in TransformFPLoadStorePair()
20041 !TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), IntVT, in TransformFPLoadStorePair()
20043 !TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), IntVT, in TransformFPLoadStorePair()
[all …]
H A DLegalizeFloatTypes.cpp1122 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in findFPToIntLibcall() local
1123 IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; in findFPToIntLibcall()
1124 ++IntVT) { in findFPToIntLibcall()
1125 Promoted = (MVT::SimpleValueType)IntVT; in findFPToIntLibcall()
H A DSelectionDAG.cpp7659 EVT IntVT = VT.getScalarType(); in getMemsetValue() local
7660 if (!IntVT.isInteger()) in getMemsetValue()
7661 IntVT = EVT::getIntegerVT(*DAG.getContext(), IntVT.getSizeInBits()); in getMemsetValue()
7663 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value); in getMemsetValue()
7668 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value, in getMemsetValue()
7669 DAG.getConstant(Magic, dl, IntVT)); in getMemsetValue()
H A DSelectionDAGBuilder.cpp251 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); in getCopyFromParts() local
252 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, in getCopyFromParts()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp162 for (MVT IntVT : {MVT::i32, MVT::i64}) { in initSPUActions()
164 setOperationAction(ISD::UREM, IntVT, Expand); in initSPUActions()
165 setOperationAction(ISD::SREM, IntVT, Expand); in initSPUActions()
166 setOperationAction(ISD::SDIVREM, IntVT, Expand); in initSPUActions()
167 setOperationAction(ISD::UDIVREM, IntVT, Expand); in initSPUActions()
170 setOperationAction(ISD::SHL_PARTS, IntVT, Expand); in initSPUActions()
171 setOperationAction(ISD::SRA_PARTS, IntVT, Expand); in initSPUActions()
172 setOperationAction(ISD::SRL_PARTS, IntVT, Expand); in initSPUActions()
176 setOperationAction(ISD::MULHU, IntVT, Expand); in initSPUActions()
177 setOperationAction(ISD::MULHS, IntVT, Expand); in initSPUActions()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp2054 EVT IntVT = MemVT.changeTypeToInteger(); in lowerKernargMemParameter() local
2066 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract); in lowerKernargMemParameter()
2955 EVT IntVT = MemVT.changeTypeToInteger(); in LowerFormalArguments() local
2970 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, DL, IntVT, Extract); in LowerFormalArguments()
5978 EVT IntVT = LoadVT.changeTypeToInteger(); in lowerIntrinsicLoad() local
6000 return getMemIntrinsicNode(Opc, DL, M->getVTList(), Ops, IntVT, in lowerIntrinsicLoad()
6121 MVT IntVT = MVT::getIntegerVT(ValSize); in lowerLaneOp() local
6176 Src0 = DAG.getAnyExtOrTrunc(IsFloat ? DAG.getBitcast(IntVT, Src0) : Src0, in lowerLaneOp()
6180 Src1 = DAG.getAnyExtOrTrunc(IsFloat ? DAG.getBitcast(IntVT, Src1) : Src1, in lowerLaneOp()
6185 Src2 = DAG.getAnyExtOrTrunc(IsFloat ? DAG.getBitcast(IntVT, Src2) : Src2, in lowerLaneOp()
[all …]
H A DAMDGPUISelLowering.cpp1911 MVT IntVT = MVT::i32; in LowerDIVREM24() local
1931 SDValue jq = DAG.getConstant(1, DL, IntVT); in LowerDIVREM24()
1982 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq); in LowerDIVREM24()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp690 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); in initActions() local
691 if (IntVT.isValid()) { in initActions()
693 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3093 MVT IntVT = ContainerVT.changeVectorElementTypeToInteger(); in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
3111 Truncated = DAG.getNode(RISCVISD::VFCVT_RM_X_F_VL, DL, IntVT, Src, Mask, in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
3116 Truncated = DAG.getNode(RISCVISD::VFCVT_RTZ_X_F_VL, DL, IntVT, Src, in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
3121 Truncated = DAG.getNode(RISCVISD::VFCVT_X_F_VL, DL, IntVT, Src, Mask, VL); in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
3201 MVT IntVT = ContainerVT.changeVectorElementTypeToInteger(); in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
3215 RISCVISD::STRICT_VFCVT_RM_X_F_VL, DL, DAG.getVTList(IntVT, MVT::Other), in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
3222 DAG.getVTList(IntVT, MVT::Other), Chain, Src, Mask, VL); in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
5470 EVT IntVT = FloatVT.changeVectorElementTypeToInteger(); in lowerCTLZ_CTTZ_ZERO_UNDEF()
5471 SDValue Bitcast = DAG.getBitcast(IntVT, FloatVal); in lowerCTLZ_CTTZ_ZERO_UNDEF()
5477 Exp = DAG.getNode(ISD::VP_SRL, DL, IntVT, Bitcas in lowerCTLZ_CTTZ_ZERO_UNDEF()
3092 MVT IntVT = ContainerVT.changeVectorElementTypeToInteger(); lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() local
3200 MVT IntVT = ContainerVT.changeVectorElementTypeToInteger(); lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND() local
5469 EVT IntVT = FloatVT.changeVectorElementTypeToInteger(); lowerCTLZ_CTTZ_ZERO_UNDEF() local
10662 MVT IntVT = VecVT.changeVectorElementTypeToInteger(); lowerVECTOR_REVERSE() local
11436 MVT IntVT = DstVT.changeVectorElementTypeToInteger(); lowerVPFPIntConvOp() local
11449 MVT IntVT = MVT::getVectorVT(MVT::getIntegerVT(DstEltSize / 2), lowerVPFPIntConvOp() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp17961 MVT IntVT = MVT::getIntegerVT(Vec.getValueType().getVectorNumElements()); in ExtractBitFromMaskVector() local
17962 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, DAG.getBitcast(IntVT, Vec)); in ExtractBitFromMaskVector()
19172 MVT IntVT = CastToInt.getSimpleValueType(); in lowerFPToIntToFP() local
19181 IntVT != MVT::i32) in lowerFPToIntToFP()
19185 unsigned IntSize = IntVT.getSizeInBits(); in lowerFPToIntToFP()
19188 MVT VecIntVT = MVT::getVectorVT(IntVT, 128 / IntSize); in lowerFPToIntToFP()
22322 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); in LowerVectorAllEqual() local
22323 if (!DAG.getTargetLoweringInfo().isTypeLegal(IntVT)) { in LowerVectorAllEqual()
22324 if (IntVT != MVT::i64) in LowerVectorAllEqual()
22326 auto SplitLHS = DAG.SplitScalar(DAG.getBitcast(IntVT, MaskBits(LHS)), DL, in LowerVectorAllEqual()
[all …]
H A DX86ISelLoweringCall.cpp1630 MVT IntVT = is64Bit() ? MVT::i64 : MVT::i32; in forwardMustTailParameters() local
1631 RegParmTypes.push_back(IntVT); in forwardMustTailParameters()
H A DX86ISelDAGToDAG.cpp1278 EVT IntVT = EVT(VecVT).changeVectorElementTypeToInteger(); in PreprocessISelDAG() local
1279 Op0 = CurDAG->getNode(ISD::BITCAST, dl, IntVT, Op0); in PreprocessISelDAG()
1280 Op1 = CurDAG->getNode(ISD::BITCAST, dl, IntVT, Op1); in PreprocessISelDAG()
1289 Res = CurDAG->getNode(Opc, dl, IntVT, Op0, Op1); in PreprocessISelDAG()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5927 MVT IntVT = MVT::getIntegerVT(VT.getScalarSizeInBits()); in lowerINSERT_VECTOR_ELT() local
5928 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements()); in lowerINSERT_VECTOR_ELT()
5931 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2); in lowerINSERT_VECTOR_ELT()
5954 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits()); in lowerEXTRACT_VECTOR_ELT() local
5955 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements()); in lowerEXTRACT_VECTOR_ELT()
5956 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, in lowerEXTRACT_VECTOR_ELT()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1024 MVT IntVT = MVT::i32; in LowerFormalArguments() local
1025 RegParmTypes.push_back(IntVT); in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4545 EVT IntVT = SrcVT.changeVectorElementTypeToInteger(); in LowerVectorFP_TO_INT_SAT() local
4546 SDValue NativeCvt = DAG.getNode(Op.getOpcode(), DL, IntVT, SrcVal, in LowerVectorFP_TO_INT_SAT()
4547 DAG.getValueType(IntVT.getScalarType())); in LowerVectorFP_TO_INT_SAT()
4551 APInt::getSignedMaxValue(SatWidth).sext(SrcElementWidth), DL, IntVT); in LowerVectorFP_TO_INT_SAT()
4552 SDValue Min = DAG.getNode(ISD::SMIN, DL, IntVT, NativeCvt, MinC); in LowerVectorFP_TO_INT_SAT()
4554 APInt::getSignedMinValue(SatWidth).sext(SrcElementWidth), DL, IntVT); in LowerVectorFP_TO_INT_SAT()
4555 Sat = DAG.getNode(ISD::SMAX, DL, IntVT, Min, MaxC); in LowerVectorFP_TO_INT_SAT()
4558 APInt::getAllOnes(SatWidth).zext(SrcElementWidth), DL, IntVT); in LowerVectorFP_TO_INT_SAT()
4559 Sat = DAG.getNode(ISD::UMIN, DL, IntVT, NativeCvt, MinC); in LowerVectorFP_TO_INT_SAT()
9945 EVT IntVT = VT.changeTypeToInteger(); in LowerFCOPYSIGN() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp7891 EVT IntVT = Op.getValueType(); in LowerGET_DYNAMIC_AREA_OFFSET() local
7898 SDVTList VTs = DAG.getVTList(IntVT); in LowerGET_DYNAMIC_AREA_OFFSET()