| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 2538 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2541 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2545 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2548 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2553 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2556 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2560 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2563 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2568 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2571 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
[all …]
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| H A D | ARMISelLowering.cpp | 18288 unsigned IntOp = N.getConstantOperandVal(1); in SearchLoopIntrinsic() local
18289 if (IntOp != Intrinsic::test_start_loop_iterations && in SearchLoopIntrinsic()
18290 IntOp != Intrinsic::loop_decrement_reg) in SearchLoopIntrinsic()
18366 unsigned IntOp = Int->getConstantOperandVal(1); in PerformHWLoopCombine() local
18379 if (IntOp == Intrinsic::test_start_loop_iterations) { in PerformHWLoopCombine()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/AsmParser/ |
| H A D | WebAssemblyAsmParser.cpp | 57 struct IntOp { struct
85 struct IntOp Int;
94 WebAssemblyOperand(SMLoc Start, SMLoc End, IntOp I) in WebAssemblyOperand()
438 Int.getLoc(), Int.getEndLoc(), WebAssemblyOperand::IntOp{Val})); in parseSingleInteger()
506 Tok.getLoc(), Tok.getEndLoc(), WebAssemblyOperand::IntOp{-1})); in checkForP2AlignIfLoadStore()
522 NameLoc, NameLoc, WebAssemblyOperand::IntOp{static_cast<int64_t>(BT)})); in addBlockTypeOperand()
576 WebAssemblyOperand::IntOp{0}); in parseFunctionTableOperand()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXIntrinsics.td | 206 multiclass VOTE<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
209 [(set regclass:$dest, (IntOp i1:$pred))]>,
219 multiclass VOTE_SYNC<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
222 [(set regclass:$dest, (IntOp imm:$mask, i1:$pred))]>,
226 [(set regclass:$dest, (IntOp i32:$mask, i1:$pred))]>,
245 multiclass MATCH_ANY_SYNC<NVPTXRegClass regclass, string ptxtype, Intrinsic IntOp,
249 [(set i32:$dest, (IntOp imm:$mask, imm:$value))]>,
253 [(set i32:$dest, (IntOp i32:$mask, imm:$value))]>,
257 [(set i32:$dest, (IntOp imm:$mask, regclass:$value))]>,
261 [(set i32:$dest, (IntOp i32:$mask, regclass:$value))]>,
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 1124 const SCEV *IntOp = SCEVPtrToIntSinkingRewriter::rewrite(Op, *this); in getLosslessPtrToIntExpr() local
1125 assert(IntOp->getType()->isIntegerTy() && in getLosslessPtrToIntExpr()
1128 return IntOp; in getLosslessPtrToIntExpr()
1134 const SCEV *IntOp = getLosslessPtrToIntExpr(Op); in getPtrToIntExpr() local
1135 if (isa<SCEVCouldNotCompute>(IntOp)) in getPtrToIntExpr()
1136 return IntOp; in getPtrToIntExpr()
1138 return getTruncateOrZeroExtend(IntOp, Ty); in getPtrToIntExpr()
8066 const SCEV *IntOp = getPtrToIntExpr(Op, DstIntTy); in createSCEV() local
8067 if (isa<SCEVCouldNotCompute>(IntOp)) in createSCEV()
8069 return IntOp; in createSCEV()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrFormats.td | 7308 Intrinsic IntOp> {
7312 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
7320 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
7328 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
7337 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
7342 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
7347 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 54792 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1); in lowerX86FPLogicOp() local
54793 return DAG.getBitcast(VT, IntOp); in lowerX86FPLogicOp()
|