Searched refs:InstrToCycle (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachinePipeliner.h | 545 std::map<SUnit *, int> InstrToCycle; variable
572 InstrToCycle.clear(); in reset()
619 std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SU); in stageScheduled()
620 if (it == InstrToCycle.end()) in stageScheduled()
628 std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SU); in cycleScheduled()
629 assert(it != InstrToCycle.end() && "Instruction hasn't been scheduled."); in cycleScheduled()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 2842 InstrToCycle.insert(std::make_pair(SU, curCycle)); in insert()
2868 std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(PrevSU); in earliestCycleInChain()
2869 if (it == InstrToCycle.end()) in earliestCycleInChain()
2891 std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SuccSU); in latestCycleInChain()
2892 if (it == InstrToCycle.end()) in latestCycleInChain()
3159 if (InstrToCycle.count(Pred.getSUnit()) && !DAG->isBackedge(SU, Pred)) in onlyHasLoopCarriedOutputOrOrderPreds()
3162 if (InstrToCycle.count(Succ.getSUnit()) && DAG->isBackedge(SU, Succ)) in onlyHasLoopCarriedOutputOrOrderPreds()
3204 NewLastCycle = std::max(NewLastCycle, InstrToCycle[&SU]); in normalizeNonPipelinedInstructions()
3211 NewCycle = std::max(InstrToCycle[Dep.getSUnit()], NewCycle); in normalizeNonPipelinedInstructions()
3213 int OldCycle = InstrToCycle[&SU]; in normalizeNonPipelinedInstructions()
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