| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | DFAPacketizer.h | 75 const InstrItineraryData *InstrItins;
82 DFAPacketizer(const InstrItineraryData *InstrItins, Automaton<uint64_t> a, in DFAPacketizer() argument
84 : InstrItins(InstrItins), A(std::move(a)), ItinActions(ItinActions) { in DFAPacketizer()
126 const InstrItineraryData *getInstrItins() const { return InstrItins; } in getInstrItins()
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| H A D | TargetSchedule.h | 35 InstrItineraryData InstrItins; variable
97 return &InstrItins; in getInstrItineraries()
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| H A D | ResourcePriorityQueue.h | 62 const InstrItineraryData* InstrItins; variable
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetSchedule.cpp | 41 return EnableSchedItins && !InstrItins.isEmpty(); in hasInstrItineraries()
49 STI->initInstrItins(InstrItins); in init()
95 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
96 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI); in getNumMicroOps()
183 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx, in computeOperandLatency()
188 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx); in computeOperandLatency()
260 return TII->getInstrLatency(&InstrItins, *MI); in computeInstrLatency()
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| H A D | PostRASchedulerList.cpp | 214 const InstrItineraryData *InstrItins = in SchedulePostRATDList() local
218 InstrItins, this); in SchedulePostRATDList()
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| H A D | TwoAddressInstructionPass.cpp | 96 const InstrItineraryData *InstrItins = nullptr; member in __anon97cd436d0111::TwoAddressInstructionImpl
270 InstrItins(Func.getSubtarget().getInstrItineraryData()), in INITIALIZE_PASS_DEPENDENCY()
284 InstrItins(Func.getSubtarget().getInstrItineraryData()), in TwoAddressInstructionImpl()
956 if (TII->getInstrLatency(InstrItins, *MI) > 1) in rescheduleMIBelowKill()
1088 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist)) in isDefTooClose()
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| H A D | MachinePipeliner.cpp | 1372 const InstrItineraryData *InstrItins; member
1377 : InstrItins(TSI.getInstrItineraryData()), STI(&TSI) {} in FuncUnitSorter()
1386 if (InstrItins && !InstrItins->isEmpty()) { in minFuncUnits()
1388 make_range(InstrItins->beginStage(SchedClass), in minFuncUnits()
1389 InstrItins->endStage(SchedClass))) { in minFuncUnits()
1432 if (InstrItins && !InstrItins->isEmpty()) { in calcCriticalResources()
1434 make_range(InstrItins->beginStage(SchedClass), in calcCriticalResources()
1435 InstrItins->endStage(SchedClass))) { in calcCriticalResources()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600Subtarget.h | 42 InstrItineraryData InstrItins; variable
66 return &InstrItins; in getInstrItineraryData()
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| H A D | R600Subtarget.cpp | 32 InstrItins(getInstrItineraryForCPU(GPU)) { in R600Subtarget()
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| H A D | GCNSubtarget.h | 66 InstrItineraryData InstrItins; variable
338 return &InstrItins; in getInstrItineraryData()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kSubtarget.h | 58 InstrItineraryData InstrItins; variable
166 return &InstrItins; in getInstrItineraryData()
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| H A D | M68kSubtarget.cpp | 102 InstrItins = getInstrItineraryForCPU(CPUName); in initializeSubtargetDependencies()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCSubtarget.h | 89 InstrItineraryData InstrItins; variable
144 return &InstrItins; in getInstrItineraryData()
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| H A D | PPCSubtarget.cpp | 100 InstrItins = getInstrItineraryForCPU(CPUName); in initSubtargetFeatures()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSubtarget.h | 211 InstrItineraryData InstrItins; variable
401 return &InstrItins; in getInstrItineraryData()
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| H A D | MipsSubtarget.cpp | 253 InstrItins = getInstrItineraryForCPU(CPUName); in initializeSubtargetDependencies()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMSubtarget.h | 196 InstrItineraryData InstrItins; variable
435 return &InstrItins; in getInstrItineraryData()
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| H A D | ARMSubtarget.cpp | 184 InstrItins = getInstrItineraryForCPU(CPUString); in initSubtargetFeatures()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.h | 108 InstrItineraryData InstrItins; variable
122 return &InstrItins; in getInstrItineraryData()
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| H A D | HexagonSubtarget.cpp | 82 InstrItins(getInstrItineraryForCPU(CPUString)) { in HexagonSubtarget()
86 assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized"); in HexagonSubtarget()
484 InstrInfo.getOperandLatency(&InstrItins, *SrcInst, 0, *DDst, UseIdx); in adjustSchedDependency()
583 &InstrItins, *SrcI, DefIdx, *DstI, OpNum); in restoreLatency()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 359 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const { in initInstrItins()
360 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles, in initInstrItins()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 51 : ScheduleDAG(mf), InstrItins(mf.getSubtarget().getInstrItineraryData()) {} in ScheduleDAGSDNodes()
632 if (!InstrItins || InstrItins->isEmpty()) { in computeLatency()
646 SU->Latency += TII->getInstrLatency(InstrItins, N); in computeLatency()
663 TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
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| H A D | ScheduleDAGSDNodes.h | 50 const InstrItineraryData *InstrItins; variable
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| H A D | ResourcePriorityQueue.cpp | 44 : Picker(this), InstrItins(IS->MF->getSubtarget().getInstrItineraryData()) { in ResourcePriorityQueue()
312 if (Packet.size() >= InstrItins->SchedModel.IssueWidth) { in reserveResources()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCSubtargetInfo.h | 220 void initInstrItins(InstrItineraryData &InstrItins) const;
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