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Searched refs:Instr (Results 1 – 25 of 155) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A DELF_aarch64.cpp198 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
199 if (!aarch64::isLDRLiteral(Instr)) in addSingleRelocation()
207 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
208 if (!aarch64::isADR(Instr)) in addSingleRelocation()
224 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
225 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
226 aarch64::getPageOffset12Shift(Instr) != 0) in addSingleRelocation()
235 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
236 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
237 aarch64::getPageOffset12Shift(Instr) != 1) in addSingleRelocation()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DCorrelatedValuePropagation.cpp746 static bool narrowSDivOrSRem(BinaryOperator *Instr, const ConstantRange &LCR, in narrowSDivOrSRem() argument
748 assert(Instr->getOpcode() == Instruction::SDiv || in narrowSDivOrSRem()
749 Instr->getOpcode() == Instruction::SRem); in narrowSDivOrSRem()
753 unsigned OrigWidth = Instr->getType()->getScalarSizeInBits(); in narrowSDivOrSRem()
775 IRBuilder<> B{Instr}; in narrowSDivOrSRem()
776 auto *TruncTy = Instr->getType()->getWithNewBitWidth(NewWidth); in narrowSDivOrSRem()
777 auto *LHS = B.CreateTruncOrBitCast(Instr->getOperand(0), TruncTy, in narrowSDivOrSRem()
778 Instr->getName() + ".lhs.trunc"); in narrowSDivOrSRem()
779 auto *RHS = B.CreateTruncOrBitCast(Instr->getOperand(1), TruncTy, in narrowSDivOrSRem()
780 Instr->getName() + ".rhs.trunc"); in narrowSDivOrSRem()
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H A DGuardWidening.cpp159 Instruction *Instr, const df_iterator<DomTreeNode *> &DFSI,
378 Instruction *Instr, const df_iterator<DomTreeNode *> &DFSI, in eliminateInstrViaWidening() argument
382 parseWidenableGuard(Instr, ChecksToHoist); in eliminateInstrViaWidening()
403 auto E = Instr->getParent() == CurBB ? find(GuardsInCurBB, Instr) in eliminateInstrViaWidening()
420 assert((i == (e - 1)) == (Instr->getParent() == CurBB) && "Bad DFS?"); in eliminateInstrViaWidening()
428 auto Score = computeWideningScore(Instr, Candidate, *WideningPoint, in eliminateInstrViaWidening()
430 LLVM_DEBUG(dbgs() << "Score between " << *Instr << " and " << *Candidate in eliminateInstrViaWidening()
440 LLVM_DEBUG(dbgs() << "Did not eliminate guard " << *Instr << "\n"); in eliminateInstrViaWidening()
444 assert(BestSoFar != Instr && "Should have never visited same guard!"); in eliminateInstrViaWidening()
445 assert(DT.dominates(BestSoFar, Instr) && "Should be!"); in eliminateInstrViaWidening()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFeatures.h21 bool IsCPSRDead(const InstrType *Instr);
24 inline bool isV8EligibleForIT(const InstrType *Instr) { in isV8EligibleForIT() argument
25 switch (Instr->getOpcode()) { in isV8EligibleForIT()
52 return IsCPSRDead(Instr); in isV8EligibleForIT()
79 return Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
84 return Instr->getOperand(0).getReg() != ARM::PC; in isV8EligibleForIT()
86 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
87 Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
90 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
91 Instr->getOperand(1).getReg() != ARM::PC; in isV8EligibleForIT()
H A DMVETPAndVPTOptimisationsPass.cpp76 MachineInstr &Instr,
574 static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) { in GetCondCode() argument
575 assert(IsVCMP(Instr.getOpcode()) && "Inst must be a VCMP"); in GetCondCode()
576 return ARMCC::CondCodes(Instr.getOperand(3).getImm()); in GetCondCode()
607 static bool IsWritingToVCCR(MachineInstr &Instr) { in IsWritingToVCCR() argument
608 if (Instr.getNumOperands() == 0) in IsWritingToVCCR()
610 MachineOperand &Dst = Instr.getOperand(0); in IsWritingToVCCR()
616 MachineRegisterInfo &RegInfo = Instr.getMF()->getRegInfo(); in IsWritingToVCCR()
630 MachineBasicBlock &MBB, MachineInstr &Instr, MachineOperand &User, in ReplaceRegisterUseWithVPNOT() argument
635 BuildMI(MBB, &Instr, Instr.getDebugLoc(), TII->get(ARM::MVE_VPNOT)) in ReplaceRegisterUseWithVPNOT()
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H A DThumb1InstrInfo.cpp180 unsigned Instr; in expandLoadStackGuard() local
182 Instr = ARM::tLDRLIT_ga_pcrel; in expandLoadStackGuard()
184 Instr = ARM::t2MOVi32imm; in expandLoadStackGuard()
186 Instr = ARM::tMOVi32imm; in expandLoadStackGuard()
188 Instr = ARM::tLDRLIT_ga_abs; in expandLoadStackGuard()
189 expandLoadStackGuardBase(MI, Instr, ARM::tLDRi); in expandLoadStackGuard()
/freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/
H A Daarch64.h362 inline bool isLoadStoreImm12(uint32_t Instr) { in isLoadStoreImm12() argument
364 return (Instr & LoadStoreImm12Mask) == 0x39000000; in isLoadStoreImm12()
367 inline bool isTestAndBranchImm14(uint32_t Instr) { in isTestAndBranchImm14() argument
369 return (Instr & TestAndBranchImm14Mask) == 0x36000000; in isTestAndBranchImm14()
372 inline bool isCondBranchImm19(uint32_t Instr) { in isCondBranchImm19() argument
374 return (Instr & CondBranchImm19Mask) == 0x54000000; in isCondBranchImm19()
377 inline bool isCompAndBranchImm19(uint32_t Instr) { in isCompAndBranchImm19() argument
379 return (Instr & CompAndBranchImm19Mask) == 0x34000000; in isCompAndBranchImm19()
382 inline bool isADR(uint32_t Instr) { in isADR() argument
384 return (Instr & ADRMask) == 0x10000000; in isADR()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp51 MachineInstr *Instr; member in __anon1f03f2b70111::RegSeqInfo
55 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { in RegSeqInfo()
57 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) { in RegSeqInfo()
58 MachineOperand &MO = Instr->getOperand(i); in RegSeqInfo()
59 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo()
70 return RSI.Instr == Instr; in operator ==()
182 Register Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
183 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
187 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector()
222 RSI->Instr->eraseFromParent(); in RebuildVector()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
94 if (isRMOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
96 else if (isSPLSOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
98 else if (isRRMOpcode(Instr.getOpcode())) { in PostOperandDecodeAdjust()
112 if (Instr.getOperand(2).isReg()) { in PostOperandDecodeAdjust()
113 Instr.getOperand(2).setReg(Lanai::R0); in PostOperandDecodeAdjust()
115 if (Instr.getOperand(2).isImm()) in PostOperandDecodeAdjust()
116 Instr.getOperand(2).setImm(0); in PostOperandDecodeAdjust()
127 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
132 LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/GlobalISel/
H A DGIMatchDagPredicate.cpp
H A DGIMatchDagPredicate.h
H A DGIMatchTree.cpp
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVectorUtils.h476 InterleaveGroup(InstTy *Instr, int32_t Stride, Align Alignment) in InterleaveGroup() argument
477 : Alignment(Alignment), InsertPos(Instr) { in InterleaveGroup()
482 Members[0] = Instr; in InterleaveGroup()
495 bool insertMember(InstTy *Instr, int32_t Index, Align NewAlign) { in insertMember() argument
533 Members[Key] = Instr; in insertMember()
547 uint32_t getIndex(const InstTy *Instr) const { in getIndex() argument
549 if (I.second == Instr) in getIndex()
649 bool isInterleaved(Instruction *Instr) const { in isInterleaved() argument
650 return InterleaveGroupMap.contains(Instr); in isInterleaved()
657 getInterleaveGroup(const Instruction *Instr) const { in getInterleaveGroup() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp68 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
165 DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
182 Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address, in getInstruction()
185 Result = decodeInstruction(DecoderTableBPF64, Instr, Insn, Address, this, in getInstruction()
190 switch (Instr.getOpcode()) { in getInstruction()
202 auto& Op = Instr.getOperand(1); in getInstruction()
212 auto Op = Instr.getOperand(0); in getInstruction()
213 Instr.clear(); in getInstruction()
214 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
215 Instr in getInstruction()
166 getInstruction(MCInst & Instr,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & CStream) const getInstruction() argument
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DDbgEntityHistoryCalculator.h78 Entry(const MachineInstr *Instr, EntryKind Kind) in Entry() argument
79 : Instr(Instr, Kind), EndIndex(NoEntry) {} in Entry()
81 const MachineInstr *getInstr() const { return Instr.getPointer(); } in getInstr()
83 EntryKind getEntryKind() const { return Instr.getInt(); } in getEntryKind()
92 PointerIntPair<const MachineInstr *, 1, EntryKind> Instr;
H A DRDFGraph.h389 using Instr = NodeAddr<InstrNode *>; variable
777 void pushAllDefs(Instr IA, DefStackMap &DM);
794 Ref getNextRelated(Instr IA, Ref RA) const;
795 Ref getNextShadow(Instr IA, Ref RA, bool Create);
797 NodeList getRelatedRefs(Instr IA, Ref RA) const;
852 Use newUse(Instr Owner, MachineOperand &Op, uint16_t Flags = NodeAttrs::None);
855 Def newDef(Instr Owner, MachineOperand &Op, uint16_t Flags = NodeAttrs::None);
856 Def newDef(Instr Owner, RegisterRef RR, uint16_t Flags = NodeAttrs::PhiRef);
863 std::pair<Ref, Ref> locateNextRef(Instr IA, Ref RA, Predicate P) const;
872 void pushClobbers(Instr IA, DefStackMap &DM);
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PromoteConstant.cpp272 static bool shouldConvertUse(const Constant *Cst, const Instruction *Instr, in shouldConvertUse() argument
276 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2) in shouldConvertUse()
280 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) in shouldConvertUse()
284 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) in shouldConvertUse()
287 if (isa<const AllocaInst>(Instr) && OpIdx > 0) in shouldConvertUse()
291 if (isa<const LoadInst>(Instr) && OpIdx > 0) in shouldConvertUse()
295 if (isa<const StoreInst>(Instr) && OpIdx > 1) in shouldConvertUse()
299 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) in shouldConvertUse()
304 if (isa<const LandingPadInst>(Instr)) in shouldConvertUse()
308 if (isa<const SwitchInst>(Instr)) in shouldConvertUse()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRemoveRedundantDebugValues.cpp138 for (auto &Instr : DbgValsToBeRemoved) { in reduceDbgValsForwardScan() local
139 LLVM_DEBUG(dbgs() << "removing "; Instr->dump()); in reduceDbgValsForwardScan()
140 Instr->eraseFromParent(); in reduceDbgValsForwardScan()
193 for (auto &Instr : DbgValsToBeRemoved) { in reduceDbgValsBackwardScan() local
194 LLVM_DEBUG(dbgs() << "removing "; Instr->dump()); in reduceDbgValsBackwardScan()
195 Instr->eraseFromParent(); in reduceDbgValsBackwardScan()
H A DMachineUniformityAnalysis.cpp32 const MachineInstr &Instr) { in markDefsDivergent() argument
37 for (auto &op : Instr.all_defs()) { in markDefsDivergent()
79 const MachineInstr &Instr) { in pushUsers() argument
80 assert(!isAlwaysUniform(Instr)); in pushUsers()
81 if (Instr.isTerminator()) in pushUsers()
83 for (const MachineOperand &op : Instr.all_defs()) { in pushUsers()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DUniformityAnalysis.cpp29 const Instruction &Instr) { in markDefsDivergent() argument
30 return markDivergent(cast<Value>(&Instr)); in markDefsDivergent()
59 const Instruction &Instr) { in pushUsers() argument
60 assert(!isAlwaysUniform(Instr)); in pushUsers()
61 if (Instr.isTerminator()) in pushUsers()
63 pushUsers(cast<Value>(&Instr)); in pushUsers()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXImageOptimizer.cpp63 for (Instruction &Instr : BB) { in runOnFunction()
64 if (CallInst *CI = dyn_cast<CallInst>(&Instr)) { in runOnFunction()
71 Changed |= replaceIsTypePSampler(Instr); in runOnFunction()
74 Changed |= replaceIsTypePSurface(Instr); in runOnFunction()
77 Changed |= replaceIsTypePTexture(Instr); in runOnFunction()
H A DNVPTXProxyRegErasure.cpp56 void replaceRegisterUsage(MachineInstr &Instr, MachineOperand &From,
107 void NVPTXProxyRegErasure::replaceRegisterUsage(MachineInstr &Instr, in replaceRegisterUsage() argument
110 for (auto &Op : Instr.uses()) { in replaceRegisterUsage()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DRegBankSelect.h207 MachineInstr &Instr;
209 /// Does the insertion point is before or after Instr.
216 return Instr; in getPointImpl()
217 return Instr.getNextNode() ? *Instr.getNextNode() in getPointImpl()
218 : Instr.getParent()->end(); in getPointImpl()
222 return *Instr.getParent(); in getInsertMBBImpl()
226 /// Create an insertion point before (\p Before=true) or after \p Instr.
227 InstrInsertPoint(MachineInstr &Instr, bool Before = true);
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCDwarf.cpp1319 void emitCFIInstruction(const MCCFIInstruction &Instr);
1328 void FrameEmitterImpl::emitCFIInstruction(const MCCFIInstruction &Instr) { in emitCFIInstruction() argument
1332 switch (Instr.getOperation()) { in emitCFIInstruction()
1334 unsigned Reg1 = Instr.getRegister(); in emitCFIInstruction()
1335 unsigned Reg2 = Instr.getRegister2(); in emitCFIInstruction()
1354 unsigned Reg = Instr.getRegister(); in emitCFIInstruction()
1362 Instr.getOperation() == MCCFIInstruction::OpAdjustCfaOffset; in emitCFIInstruction()
1367 CFAOffset += Instr.getOffset(); in emitCFIInstruction()
1369 CFAOffset = Instr.getOffset(); in emitCFIInstruction()
1376 unsigned Reg = Instr.getRegister(); in emitCFIInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DFPEnv.cpp90 Intrinsic::ID getConstrainedIntrinsicID(const Instruction &Instr) { in getConstrainedIntrinsicID() argument
92 switch (Instr.getOpcode()) { in getConstrainedIntrinsicID()
110 if (auto *IntrinCall = dyn_cast<IntrinsicInst>(&Instr)) { in getConstrainedIntrinsicID()

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