Home
last modified time | relevance | path

Searched refs:Instr (Results 1 – 25 of 159) sorted by relevance

1234567

/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A Daarch64.cpp105 uint32_t Instr = MOVGPR64Template; in writeMovRegRegSeq() local
106 Instr |= DstReg << DstRegIndex; in writeMovRegRegSeq()
107 Instr |= SrcReg << SrcRegIndex; in writeMovRegRegSeq()
108 return Append(Instr); in writeMovRegRegSeq()
131 uint32_t Instr = MovRegImm64Template; in writeMovRegImm64Seq() local
132 Instr |= PreserveRegValue << PreserveBitIndex; in writeMovRegImm64Seq()
133 Instr |= (I << ShiftBitsIndex); in writeMovRegImm64Seq()
134 Instr |= ImmBits << ImmBitsIndex; in writeMovRegImm64Seq()
135 Instr |= Reg; in writeMovRegImm64Seq()
136 if (auto Err = Append(Instr)) in writeMovRegImm64Seq()
[all …]
H A DELF_aarch64.cpp279 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
280 if (!aarch64::isLDRLiteral(Instr)) in addSingleRelocation()
288 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
289 if (!aarch64::isADR(Instr)) in addSingleRelocation()
305 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
306 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
307 aarch64::getPageOffset12Shift(Instr) != 0) in addSingleRelocation()
316 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
317 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
318 aarch64::getPageOffset12Shift(Instr) != 1) in addSingleRelocation()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFeatures.h21 bool IsCPSRDead(const InstrType *Instr);
24 inline bool isV8EligibleForIT(const InstrType *Instr) { in isV8EligibleForIT() argument
25 switch (Instr->getOpcode()) { in isV8EligibleForIT()
52 return IsCPSRDead(Instr); in isV8EligibleForIT()
79 return Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
84 return Instr->getOperand(0).getReg() != ARM::PC; in isV8EligibleForIT()
86 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
87 Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
90 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
91 Instr->getOperand(1).getReg() != ARM::PC; in isV8EligibleForIT()
H A DMVETPAndVPTOptimisationsPass.cpp75 MachineInstr &Instr,
572 static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) { in GetCondCode() argument
573 assert(IsVCMP(Instr.getOpcode()) && "Inst must be a VCMP"); in GetCondCode()
574 return ARMCC::CondCodes(Instr.getOperand(3).getImm()); in GetCondCode()
605 static bool IsWritingToVCCR(MachineInstr &Instr) { in IsWritingToVCCR() argument
606 if (Instr.getNumOperands() == 0) in IsWritingToVCCR()
608 MachineOperand &Dst = Instr.getOperand(0); in IsWritingToVCCR()
614 MachineRegisterInfo &RegInfo = Instr.getMF()->getRegInfo(); in IsWritingToVCCR()
628 MachineBasicBlock &MBB, MachineInstr &Instr, MachineOperand &User, in ReplaceRegisterUseWithVPNOT() argument
633 BuildMI(MBB, &Instr, Instr.getDebugLoc(), TII->get(ARM::MVE_VPNOT)) in ReplaceRegisterUseWithVPNOT()
[all …]
H A DThumb1InstrInfo.cpp180 unsigned Instr; in expandLoadStackGuard() local
182 Instr = ARM::tLDRLIT_ga_pcrel; in expandLoadStackGuard()
184 Instr = ARM::t2MOVi32imm; in expandLoadStackGuard()
186 Instr = ARM::tMOVi32imm; in expandLoadStackGuard()
188 Instr = ARM::tLDRLIT_ga_abs; in expandLoadStackGuard()
189 expandLoadStackGuardBase(MI, Instr, ARM::tLDRi); in expandLoadStackGuard()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DCorrelatedValuePropagation.cpp768 static bool narrowSDivOrSRem(BinaryOperator *Instr, const ConstantRange &LCR, in narrowSDivOrSRem() argument
770 assert(Instr->getOpcode() == Instruction::SDiv || in narrowSDivOrSRem()
771 Instr->getOpcode() == Instruction::SRem); in narrowSDivOrSRem()
775 unsigned OrigWidth = Instr->getType()->getScalarSizeInBits(); in narrowSDivOrSRem()
797 IRBuilder<> B{Instr}; in narrowSDivOrSRem()
798 auto *TruncTy = Instr->getType()->getWithNewBitWidth(NewWidth); in narrowSDivOrSRem()
799 auto *LHS = B.CreateTruncOrBitCast(Instr->getOperand(0), TruncTy, in narrowSDivOrSRem()
800 Instr->getName() + ".lhs.trunc"); in narrowSDivOrSRem()
801 auto *RHS = B.CreateTruncOrBitCast(Instr->getOperand(1), TruncTy, in narrowSDivOrSRem()
802 Instr->getName() + ".rhs.trunc"); in narrowSDivOrSRem()
[all …]
H A DGuardWidening.cpp158 Instruction *Instr, const df_iterator<DomTreeNode *> &DFSI,
377 Instruction *Instr, const df_iterator<DomTreeNode *> &DFSI, in eliminateInstrViaWidening() argument
381 parseWidenableGuard(Instr, ChecksToHoist); in eliminateInstrViaWidening()
402 auto E = Instr->getParent() == CurBB ? find(GuardsInCurBB, Instr) in eliminateInstrViaWidening()
419 assert((i == (e - 1)) == (Instr->getParent() == CurBB) && "Bad DFS?"); in eliminateInstrViaWidening()
427 auto Score = computeWideningScore(Instr, Candidate, *WideningPoint, in eliminateInstrViaWidening()
429 LLVM_DEBUG(dbgs() << "Score between " << *Instr << " and " << *Candidate in eliminateInstrViaWidening()
439 LLVM_DEBUG(dbgs() << "Did not eliminate guard " << *Instr << "\n"); in eliminateInstrViaWidening()
443 assert(BestSoFar != Instr && "Should have never visited same guard!"); in eliminateInstrViaWidening()
444 assert(DT.dominates(BestSoFar, Instr) && "Should be!"); in eliminateInstrViaWidening()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/
H A DDWARFCFIPrinter.cpp43 const CFIProgram::Instruction &Instr, in printOperand() argument
47 uint8_t Opcode = Instr.Opcode; in printOperand()
102 assert(Instr.Expression && "missing DWARFExpression object"); in printOperand()
104 printDwarfExpression(&Instr.Expression.value(), OS, DumpOpts, nullptr); in printOperand()
113 for (const auto &Instr : P) { in printCFIProgram() local
114 uint8_t Opcode = Instr.Opcode; in printCFIProgram()
117 for (size_t i = 0; i < Instr.Ops.size(); ++i) in printCFIProgram()
118 printOperand(OS, DumpOpts, P, Instr, i, Instr.Ops[i], Address); in printCFIProgram()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp51 MachineInstr *Instr; member in __anon1f03f2b70111::RegSeqInfo
55 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { in RegSeqInfo()
57 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) { in RegSeqInfo()
58 MachineOperand &MO = Instr->getOperand(i); in RegSeqInfo()
59 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo()
70 return RSI.Instr == Instr; in operator ==()
181 Register Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
182 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
186 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector()
221 RSI->Instr->eraseFromParent(); in RebuildVector()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/
H A Daarch64.h425 inline bool isLoadStoreImm12(uint32_t Instr) { in isLoadStoreImm12() argument
427 return (Instr & LoadStoreImm12Mask) == 0x39000000; in isLoadStoreImm12()
430 inline bool isTestAndBranchImm14(uint32_t Instr) { in isTestAndBranchImm14() argument
432 return (Instr & TestAndBranchImm14Mask) == 0x36000000; in isTestAndBranchImm14()
435 inline bool isCondBranchImm19(uint32_t Instr) { in isCondBranchImm19() argument
437 return (Instr & CondBranchImm19Mask) == 0x54000000; in isCondBranchImm19()
440 inline bool isCompAndBranchImm19(uint32_t Instr) { in isCompAndBranchImm19() argument
442 return (Instr & CompAndBranchImm19Mask) == 0x34000000; in isCompAndBranchImm19()
445 inline bool isADR(uint32_t Instr) { in isADR() argument
447 return (Instr & ADRMask) == 0x10000000; in isADR()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp95 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
99 if (isRMOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
101 else if (isSPLSOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
103 else if (isRRMOpcode(Instr.getOpcode())) { in PostOperandDecodeAdjust()
117 if (Instr.getOperand(2).isReg()) { in PostOperandDecodeAdjust()
118 Instr.getOperand(2).setReg(Lanai::R0); in PostOperandDecodeAdjust()
120 if (Instr.getOperand(2).isImm()) in PostOperandDecodeAdjust()
121 Instr.getOperand(2).setImm(0); in PostOperandDecodeAdjust()
132 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
137 LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/GlobalISel/
H A DGIMatchDagPredicate.cpp
H A DGIMatchDagPredicate.h
H A DGIMatchTree.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp69 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
166 DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
183 Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address, in getInstruction()
186 Result = decodeInstruction(DecoderTableBPF64, Instr, Insn, Address, this, in getInstruction()
191 switch (Instr.getOpcode()) { in getInstruction()
203 auto& Op = Instr.getOperand(1); in getInstruction()
213 auto Op = Instr.getOperand(0); in getInstruction()
214 Instr.clear(); in getInstruction()
215 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
216 Instr.addOperand(Op); in getInstruction()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DDbgEntityHistoryCalculator.h78 Entry(const MachineInstr *Instr, EntryKind Kind) in Entry() argument
79 : Instr(Instr, Kind), EndIndex(NoEntry) {} in Entry()
81 const MachineInstr *getInstr() const { return Instr.getPointer(); } in getInstr()
83 EntryKind getEntryKind() const { return Instr.getInt(); } in getEntryKind()
92 PointerIntPair<const MachineInstr *, 1, EntryKind> Instr;
H A DRDFGraph.h389 using Instr = NodeAddr<InstrNode *>; variable
777 void pushAllDefs(Instr IA, DefStackMap &DM);
794 Ref getNextRelated(Instr IA, Ref RA) const;
795 Ref getNextShadow(Instr IA, Ref RA, bool Create);
797 NodeList getRelatedRefs(Instr IA, Ref RA) const;
852 Use newUse(Instr Owner, MachineOperand &Op, uint16_t Flags = NodeAttrs::None);
855 Def newDef(Instr Owner, MachineOperand &Op, uint16_t Flags = NodeAttrs::None);
856 Def newDef(Instr Owner, RegisterRef RR, uint16_t Flags = NodeAttrs::PhiRef);
863 std::pair<Ref, Ref> locateNextRef(Instr IA, Ref RA, Predicate P) const;
873 void pushClobbers(Instr IA, DefStackMap &DM);
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PromoteConstant.cpp268 static bool shouldConvertUse(const Constant *Cst, const Instruction *Instr, in shouldConvertUse() argument
272 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2) in shouldConvertUse()
276 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) in shouldConvertUse()
280 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) in shouldConvertUse()
283 if (isa<const AllocaInst>(Instr) && OpIdx > 0) in shouldConvertUse()
287 if (isa<const LoadInst>(Instr) && OpIdx > 0) in shouldConvertUse()
291 if (isa<const StoreInst>(Instr) && OpIdx > 1) in shouldConvertUse()
295 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) in shouldConvertUse()
300 if (isa<const LandingPadInst>(Instr)) in shouldConvertUse()
304 if (isa<const SwitchInst>(Instr)) in shouldConvertUse()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVectorUtils.h531 InterleaveGroup(InstTy *Instr, int32_t Stride, Align Alignment) in InterleaveGroup() argument
532 : Alignment(Alignment), InsertPos(Instr) { in InterleaveGroup()
537 Members[0] = Instr; in InterleaveGroup()
550 bool insertMember(InstTy *Instr, int32_t Index, Align NewAlign) { in insertMember() argument
588 Members[Key] = Instr; in insertMember()
602 uint32_t getIndex(const InstTy *Instr) const { in getIndex() argument
604 if (I.second == Instr) in getIndex()
704 bool isInterleaved(Instruction *Instr) const { in isInterleaved() argument
705 return InterleaveGroupMap.contains(Instr); in isInterleaved()
712 getInterleaveGroup(const Instruction *Instr) const { in getInterleaveGroup() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRemoveRedundantDebugValues.cpp141 for (auto &Instr : DbgValsToBeRemoved) { in reduceDbgValsForwardScan() local
142 LLVM_DEBUG(dbgs() << "removing "; Instr->dump()); in reduceDbgValsForwardScan()
143 Instr->eraseFromParent(); in reduceDbgValsForwardScan()
196 for (auto &Instr : DbgValsToBeRemoved) { in reduceDbgValsBackwardScan() local
197 LLVM_DEBUG(dbgs() << "removing "; Instr->dump()); in reduceDbgValsBackwardScan()
198 Instr->eraseFromParent(); in reduceDbgValsBackwardScan()
H A DMachineUniformityAnalysis.cpp33 const MachineInstr &Instr) { in markDefsDivergent() argument
38 for (auto &op : Instr.all_defs()) { in markDefsDivergent()
80 const MachineInstr &Instr) { in pushUsers() argument
81 assert(!isAlwaysUniform(Instr)); in pushUsers()
82 if (Instr.isTerminator()) in pushUsers()
84 for (const MachineOperand &op : Instr.all_defs()) { in pushUsers()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DUniformityAnalysis.cpp28 const Instruction &Instr) { in markDefsDivergent() argument
29 return markDivergent(cast<Value>(&Instr)); in markDefsDivergent()
58 const Instruction &Instr) { in pushUsers() argument
59 assert(!isAlwaysUniform(Instr)); in pushUsers()
60 if (Instr.isTerminator()) in pushUsers()
62 pushUsers(cast<Value>(&Instr)); in pushUsers()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXImageOptimizer.cpp62 for (Instruction &Instr : BB) { in runOnFunction()
63 if (CallInst *CI = dyn_cast<CallInst>(&Instr)) { in runOnFunction()
70 Changed |= replaceIsTypePSampler(Instr); in runOnFunction()
73 Changed |= replaceIsTypePSurface(Instr); in runOnFunction()
76 Changed |= replaceIsTypePTexture(Instr); in runOnFunction()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DRegBankSelect.h207 MachineInstr &Instr;
216 return Instr; in getPointImpl()
217 return Instr.getNextNode() ? *Instr.getNextNode() in getPointImpl()
218 : Instr.getParent()->end(); in getPointImpl()
222 return *Instr.getParent(); in getInsertMBBImpl()
227 InstrInsertPoint(MachineInstr &Instr, bool Before = true);
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCDwarf.cpp1354 void emitCFIInstruction(const MCCFIInstruction &Instr);
1363 void FrameEmitterImpl::emitCFIInstruction(const MCCFIInstruction &Instr) { in emitCFIInstruction() argument
1367 switch (Instr.getOperation()) { in emitCFIInstruction()
1369 unsigned Reg1 = Instr.getRegister(); in emitCFIInstruction()
1370 unsigned Reg2 = Instr.getRegister2(); in emitCFIInstruction()
1393 unsigned Reg = Instr.getRegister(); in emitCFIInstruction()
1401 Instr.getOperation() == MCCFIInstruction::OpAdjustCfaOffset; in emitCFIInstruction()
1406 CFAOffset += Instr.getOffset(); in emitCFIInstruction()
1408 CFAOffset = Instr.getOffset(); in emitCFIInstruction()
1415 unsigned Reg = Instr.getRegister(); in emitCFIInstruction()
[all …]

1234567