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Searched refs:InstRef (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DScheduler.h37 virtual bool compare(const InstRef &Lhs, const InstRef &Rhs) const = 0;
44 int computeRank(const InstRef &Lhs) const { in computeRank()
52 bool compare(const InstRef &Lhs, const InstRef &Rhs) const override { in compare()
112 std::vector<InstRef> WaitSet;
113 std::vector<InstRef> PendingSet;
114 std::vector<InstRef> ReadySet;
115 std::vector<InstRef> IssuedSet;
139 InstRef &IR,
145 void updateIssuedSet(SmallVectorImpl<InstRef> &Executed);
150 bool promoteToReadySet(SmallVectorImpl<InstRef> &Ready);
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H A DLSUnit.h88 virtual Status isAvailable(const InstRef &IR) const = 0;
96 virtual unsigned dispatch(const InstRef &IR) = 0;
104 virtual bool isReady(const InstRef &IR) const = 0;
108 virtual bool isPending(const InstRef &IR) const = 0;
112 virtual bool isWaiting(const InstRef &IR) const = 0;
114 virtual bool hasDependentUsers(const InstRef &IR) const = 0;
118 virtual void onInstructionExecuted(const InstRef &IR) = 0;
124 virtual void onInstructionRetired(const InstRef &IR) = 0;
126 virtual void onInstructionIssued(const InstRef &IR) = 0;
260 InstRef CriticalMemoryInstruction;
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H A DRetireControlUnit.h52 InstRef IR;
91 unsigned dispatch(const InstRef &IS);
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/Stages/
H A DInOrderIssueStage.h37 InstRef IR;
45 const InstRef &getInstruction() const { return IR; } in getInstruction()
46 InstRef &getInstruction() { return IR; } in getInstruction()
50 void update(const InstRef &Inst, unsigned Cycles, StallKind SK);
62 SmallVector<InstRef, 4> IssuedInst;
70 InstRef CarriedOver;
88 bool canExecute(const InstRef &IR);
91 Error tryIssue(InstRef &IR);
103 void notifyInstructionIssued(const InstRef &IR,
105 void notifyInstructionDispatched(const InstRef &IR, unsigned Ops,
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H A DExecuteStage.h37 Error issueInstruction(InstRef &IR);
44 Error handleInstructionEliminated(InstRef &IR);
62 bool isAvailable(const InstRef &IR) const override;
73 Error execute(InstRef &IR) override;
75 void notifyInstructionIssued(const InstRef &IR,
77 void notifyInstructionExecuted(const InstRef &IR) const;
78 void notifyInstructionPending(const InstRef &IR) const;
79 void notifyInstructionReady(const InstRef &IR) const;
83 void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const;
H A DDispatchStage.h53 InstRef CarriedOver;
58 bool checkRCU(const InstRef &IR) const;
59 bool checkPRF(const InstRef &IR) const;
60 bool canDispatch(const InstRef &IR) const;
61 Error dispatch(InstRef IR);
63 void notifyInstructionDispatched(const InstRef &IR,
72 bool isAvailable(const InstRef &IR) const override;
78 Error execute(InstRef &IR) override;
H A DStage.h26 class InstRef; variable
43 virtual bool isAvailable(const InstRef &IR) const { return true; } in isAvailable()
59 virtual Error execute(InstRef &IR) = 0;
66 bool checkNextStage(const InstRef &IR) const { in checkNextStage()
74 Error moveToTheNextStage(InstRef &IR) { in moveToTheNextStage()
H A DMicroOpQueueStage.h27 SmallVector<InstRef, 8> Buffer;
54 unsigned getNormalizedOpcodes(const InstRef &IR) const { in getNormalizedOpcodes()
67 bool isAvailable(const InstRef &IR) const override { in isAvailable()
80 Error execute(InstRef &IR) override;
H A DEntryStage.h28 InstRef CurrentInstruction;
42 bool isAvailable(const InstRef &IR) const override;
44 Error execute(InstRef &IR) override;
H A DRetireStage.h44 Error execute(InstRef &IR) override;
45 void notifyInstructionRetired(const InstRef &IR) const;
/freebsd/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DExecuteStage.cpp43 bool ExecuteStage::isAvailable(const InstRef &IR) const { in isAvailable()
53 Error ExecuteStage::issueInstruction(InstRef &IR) { in issueInstruction()
55 SmallVector<InstRef, 4> Pending; in issueInstruction()
56 SmallVector<InstRef, 4> Ready; in issueInstruction()
72 for (const InstRef &I : Pending) in issueInstruction()
75 for (const InstRef &I : Ready) in issueInstruction()
81 InstRef IR = HWS.select(); in issueReadyInstructions()
95 SmallVector<InstRef, 4> Executed; in cycleStart()
96 SmallVector<InstRef, 4> Pending; in cycleStart()
97 SmallVector<InstRef, 4> Ready; in cycleStart()
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H A DInOrderIssueStage.cpp30 void StallInfo::update(const InstRef &Inst, unsigned Cycles, StallKind SK) { in update()
60 bool InOrderIssueStage::isAvailable(const InstRef &IR) const { in isAvailable()
79 static bool hasResourceHazard(const ResourceManager &RM, const InstRef &IR) { in hasResourceHazard()
88 static unsigned findFirstWriteBackCycle(const InstRef &IR) { in findFirstWriteBackCycle()
105 const InstRef &IR) { in checkRegisterHazard()
115 bool InOrderIssueStage::canExecute(const InstRef &IR) { in canExecute()
169 void InOrderIssueStage::notifyInstructionIssued(const InstRef &IR, in notifyInstructionIssued()
179 const InstRef &IR, unsigned Ops, ArrayRef<unsigned> UsedRegs) { in notifyInstructionDispatched()
186 void InOrderIssueStage::notifyInstructionExecuted(const InstRef &IR) { in notifyInstructionExecuted()
192 void InOrderIssueStage::notifyInstructionRetired(const InstRef &IR, in notifyInstructionRetired()
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H A DDispatchStage.cpp37 void DispatchStage::notifyInstructionDispatched(const InstRef &IR, in notifyInstructionDispatched()
45 bool DispatchStage::checkPRF(const InstRef &IR) const { in checkPRF()
61 bool DispatchStage::checkRCU(const InstRef &IR) const { in checkRCU()
70 bool DispatchStage::canDispatch(const InstRef &IR) const { in canDispatch()
77 Error DispatchStage::dispatch(InstRef IR) { in dispatch()
149 CarriedOver = InstRef(); in cycleStart()
153 bool DispatchStage::isAvailable(const InstRef &IR) const { in isAvailable()
173 Error DispatchStage::execute(InstRef &IR) { in execute()
H A DEntryStage.cpp25 bool EntryStage::isAvailable(const InstRef & /* unused */) const { in isAvailable()
41 CurrentInstruction = InstRef(SR.first, Inst.get()); in getNextInstruction()
47 llvm::Error EntryStage::execute(InstRef & /*unused */) { in execute() argument
H A DMicroOpQueueStage.cpp22 InstRef IR = Buffer[CurrentInstructionSlotIdx]; in moveInstructions()
46 Error MicroOpQueueStage::execute(InstRef &IR) { in execute()
H A DRetireStage.cpp49 llvm::Error RetireStage::execute(InstRef &IR) { in execute()
60 void RetireStage::notifyInstructionRetired(const InstRef &IR) const { in notifyInstructionRetired()
/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp40 Scheduler::Status Scheduler::isAvailable(const InstRef &IR) { in isAvailable()
71 InstRef &IR, in issueInstructionImpl()
101 InstRef &IR, in issueInstruction()
103 SmallVectorImpl<InstRef> &PendingInstructions, in issueInstruction()
104 SmallVectorImpl<InstRef> &ReadyInstructions) { in issueInstruction()
120 bool Scheduler::promoteToReadySet(SmallVectorImpl<InstRef> &Ready) { in promoteToReadySet()
125 InstRef &IR = *I; in promoteToReadySet()
156 bool Scheduler::promoteToPendingSet(SmallVectorImpl<InstRef> &Pending) { in promoteToPendingSet()
161 InstRef &IR = *I; in promoteToPendingSet()
193 InstRef Scheduler::select() { in select()
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H A DLSUnit.cpp69 unsigned LSUnit::dispatch(const InstRef &IR) { in dispatch()
194 LSUnit::Status LSUnit::isAvailable(const InstRef &IR) const { in isAvailable()
203 void LSUnit::onInstructionRetired(const InstRef &IR) { in onInstructionRetired()
222 void LSUnit::onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted()
H A DRetireControlUnit.cpp43 unsigned RetireControlUnit::dispatch(const InstRef &IR) { in dispatch()
85 Current = { InstRef(), 0U, false }; in consumeCurrentToken()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DHWEventListener.h53 HWInstructionEvent(unsigned type, const InstRef &Inst) in HWInstructionEvent()
60 const InstRef &IR;
71 HWInstructionIssuedEvent(const InstRef &IR, ArrayRef<ResourceUse> UR) in HWInstructionIssuedEvent()
79 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent()
100 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
126 HWStallEvent(unsigned type, const InstRef &Inst) : Type(type), IR(Inst) {} in HWStallEvent()
132 const InstRef &IR;
150 HWPressureEvent(GenericReason reason, ArrayRef<InstRef> Insts,
158 ArrayRef<InstRef> AffectedInstructions;
178 virtual void onReservedBuffers(const InstRef &Inst, in onReservedBuffers()
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H A DInstruction.h721 class InstRef {
725 InstRef() : Data(std::make_pair(0, nullptr)) {} in InstRef() function
726 InstRef(unsigned Index, Instruction *I) : Data(std::make_pair(Index, I)) {} in InstRef() function
728 bool operator==(const InstRef &Other) const { return Data == Other.Data; }
729 bool operator!=(const InstRef &Other) const { return Data != Other.Data; }
730 bool operator<(const InstRef &Other) const {
750 inline raw_ostream &operator<<(raw_ostream &OS, const InstRef &IR) {
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.h81 unsigned handleWaitCnt(ArrayRef<InstRef> IssuedInst, const InstRef &IR);
85 void computeWaitCnt(const InstRef &IR, unsigned &Vmcnt, unsigned &Expcnt,
100 unsigned checkCustomHazard(ArrayRef<InstRef> IssuedInst,
101 const InstRef &IR) override;
H A DAMDGPUCustomBehaviour.cpp69 unsigned AMDGPUCustomBehaviour::checkCustomHazard(ArrayRef<InstRef> IssuedInst, in checkCustomHazard()
70 const InstRef &IR) { in checkCustomHazard()
105 unsigned AMDGPUCustomBehaviour::handleWaitCnt(ArrayRef<InstRef> IssuedInst, in handleWaitCnt()
106 const InstRef &IR) { in handleWaitCnt()
127 for (const InstRef &PrevIR : IssuedInst) { in handleWaitCnt()
177 void AMDGPUCustomBehaviour::computeWaitCnt(const InstRef &IR, unsigned &Vmcnt, in computeWaitCnt()
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DSchedulerStatistics.h82 void onReservedBuffers(const InstRef &IR,
87 void onReleasedBuffers(const InstRef &IR,
/freebsd/contrib/llvm-project/llvm/lib/MCA/
H A DCustomBehaviour.cpp21 unsigned CustomBehaviour::checkCustomHazard(ArrayRef<InstRef> IssuedInst, in checkCustomHazard()
22 const InstRef &IR) { in checkCustomHazard()

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