| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCInst.cpp | 92 StringRef InstName = Printer ? Printer->getOpcodeName(getOpcode()) : ""; in dump_pretty() local
93 dump_pretty(OS, InstName, Separator, Ctx); in dump_pretty()
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| /freebsd/contrib/llvm-project/llvm/tools/llvm-tapi-diff/ |
| H A D | DiffEngine.h | |
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | VarLenCodeEmitterGen.cpp | 298 std::string InstName = in run() local
302 CaseMap[Case].push_back(std::move(InstName)); in run()
315 for (const auto &InstName : InstList) in run() local
316 OS << LS << " case " << InstName << ":"; in run()
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| H A D | CodeGenSchedule.cpp | 137 StringRef InstName = Inst->TheDef->getName(); in apply() local
138 if (InstName.starts_with(Prefix) && in apply()
139 (!Regexpr || Regexpr->match(InstName.substr(Prefix.size())))) { in apply()
165 StringRef InstName = Inst->TheDef->getName(); in apply() local
166 if (!Regexpr || Regexpr->match(InstName.substr(Prefix.size()))) { in apply()
865 StringRef InstName = Inst->TheDef->getName(); in collectSchedClasses() local
883 dbgs() << "Itinerary for " << InstName << ": " in collectSchedClasses()
889 dbgs() << "SchedRW machine model for " << InstName; in collectSchedClasses()
902 << InstName); in collectSchedClasses()
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| H A D | CodeGenDAGPatterns.cpp | 2510 static void emitTooManyOperandsError(TreePattern &TP, StringRef InstName, in emitTooManyOperandsError() argument
2512 TP.error("Instruction '" + InstName + "' was provided " + Twine(Actual) + in emitTooManyOperandsError()
2516 static void emitTooFewOperandsError(TreePattern &TP, StringRef InstName, in emitTooFewOperandsError() argument
2518 TP.error("Instruction '" + InstName + "' expects more than the provided " + in emitTooFewOperandsError()
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| /freebsd/contrib/llvm-project/clang/utils/TableGen/ |
| H A D | RISCVVEmitter.cpp | 191 static unsigned getSegInstLog2SEW(StringRef InstName) { in getSegInstLog2SEW() argument
195 if (InstName.starts_with("vloxseg") || InstName.starts_with("vluxseg") || in getSegInstLog2SEW()
196 InstName.starts_with("vsoxseg") || InstName.starts_with("vsuxseg")) in getSegInstLog2SEW()
244 return SegInsts.lookup(InstName); in getSegInstLog2SEW()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeEmitterGen.cpp | 547 std::string InstName = in run() local
552 CaseMap[Case].push_back(InstName); in run()
553 BitOffsetCaseMap[BitOffsetCase].push_back(std::move(InstName)); in run()
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| H A D | GlobalISelCombinerEmitter.cpp | 1301 for (auto InstName : FI->copy_flags()) { in checkSemantics() local
1302 auto It = MatchPats.find(InstName); in checkSemantics()
1304 PrintError("unknown instruction '$" + InstName + in checkSemantics()
1311 "'$" + InstName + in checkSemantics()
2098 for (StringRef InstName : FI->copy_flags()) in emitInstructionApplyPattern() local
2099 DstMI.addCopiedMIFlags(M.getInstructionMatcher(InstName)); in emitInstructionApplyPattern()
2204 StringRef InstName = CGP->getInst().TheDef->getName(); in isLiteralImm() local
2205 return (InstName == "G_CONSTANT" || InstName == "G_FCONSTANT") && in isLiteralImm()
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| H A D | GlobalISelEmitter.cpp | 1937 StringRef InstName = Inst.TheDef->getName(); in inferRegClassFromInstructionPattern() local
1938 if (InstName == "REG_SEQUENCE") { in inferRegClassFromInstructionPattern()
1947 if (InstName == "COPY_TO_REGCLASS") { in inferRegClassFromInstructionPattern()
1956 if (InstName == "INSERT_SUBREG") { in inferRegClassFromInstructionPattern()
1967 if (InstName == "EXTRACT_SUBREG") { in inferRegClassFromInstructionPattern()
1988 if (InstName == "SUBREG_TO_REG") { in inferRegClassFromInstructionPattern()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/AsmParser/ |
| H A D | WebAssemblyAsmParser.cpp | 476 bool checkForP2AlignIfLoadStore(OperandVector &Operands, StringRef InstName) { in checkForP2AlignIfLoadStore() argument
478 auto IsLoadStore = InstName.contains(".load") || in checkForP2AlignIfLoadStore()
479 InstName.contains(".store") || in checkForP2AlignIfLoadStore()
480 InstName.contains("prefetch"); in checkForP2AlignIfLoadStore()
481 auto IsAtomic = InstName.contains("atomic."); in checkForP2AlignIfLoadStore()
497 auto IsLoadStoreLane = InstName.contains("_lane"); in checkForP2AlignIfLoadStore()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEInstrPatternsVec.td | 123 class Mask_Binary<ValueType MaskVT, SDPatternOperator MaskOp, string InstName> :
124 Pat<(MaskVT (MaskOp MaskVT:$ma, MaskVT:$mb)), (!cast<Instruction>(InstName#"mm") $ma, $mb)>;
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | arm_neon.td | 347 let InstName = "vcge" in
350 let InstName = "vcgt" in
352 let InstName = "vacge" in {
356 let InstName = "vacgt" in {
548 let InstName = "vmov" in
555 let InstName = "vmov" in
568 let InstName = "vmov" in {
576 let InstName = "" in
591 let InstName = "vmov" in {
621 let InstName = "vtbl" in {
[all …]
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| H A D | arm_neon_incl.td | 284 string InstName = "";
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/GlobalISel/ |
| H A D | Patterns.cpp | 364 void MIFlagsInfo::addCopyFlag(StringRef InstName) { CopyF.insert(InstName); } in addCopyFlag() argument
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| H A D | Patterns.h | 435 void addCopyFlag(StringRef InstName);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVModuleAnalysis.cpp | 1692 std::string InstName; in addInstrRequirements() local
1695 InstName = "OpCooperativeMatrixPrefetchINTEL"; in addInstrRequirements()
1698 InstName = "OpCooperativeMatrixLoadCheckedINTEL"; in addInstrRequirements()
1701 InstName = "OpCooperativeMatrixStoreCheckedINTEL"; in addInstrRequirements()
1707 InstName + " instruction requires the " in addInstrRequirements()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | Debugify.cpp | 508 auto InstName = Instruction::getOpcodeName(Instr->getOpcode()); in checkInstructions() local
515 {"instr", InstName}, in checkInstructions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXIntrinsics.td | 788 class PREFETCH_INTRS<string InstName> :
790 InstName,
792 !subst(".", "_", InstName))) addr:$addr)]>,
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